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qwen3-coder:30b | RAG off

06_reset_domain_crossing / task_63 | delayed_reset_release

benchmarkilyasov
task_idilyasov/06_reset_domain_crossing/task_63
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260426_175047_007550_9b8266

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260426_175047_007550_9b8266__sample_1
generated.v preview 
module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

reg srst_n_reg;
reg [1:0] delay_counter;
reg init_pulse_reg;

assign srst_n = srst_n_reg;
assign init_pulse = init_pulse_reg;

reg arst_n_sync1, arst_n_sync2;
reg srst_n_sync1, srst_n_sync2;

always @(posedge clk) begin
    arst_n_sync1 <= arst_n;
    arst_n_sync2 <= arst_n_sync1;
    srst_n_sync1 <= srst_n_reg;
    srst_n_sync2 <= srst_n_sync1;
end

always @(posedge clk) begin
    if (!arst_n) begin
        srst_n_reg <= 0;
        delay_counter <= 0;
        init_pulse_reg <= 0;
    end else if (srst_n_sync2 && !srst_n_sync1) begin
        if (delay_counter == 0) begin
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset released before the extra delay window started.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260426_175047_007550_9b8266__sample_2
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg srst_n_reg;
    reg init_pulse_reg;
    reg [1:0] delay_counter;
    reg sync_arst_n;
    reg sync_arst_n_d1;
    reg reset_release_ready;
    reg reset_release_requested;

    assign srst_n = srst_n_reg;
    assign init_pulse = init_pulse_reg;

    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            srst_n_reg <= 0;
            init_pulse_reg <= 0;
            delay_counter <= 0;
            sync_arst_n <= 0;
            sync_arst_n_d1 <= 0;
            reset_release_ready <= 0;
            reset_release_requested <= 0;
        end else begin
            sync_arst_n_d1 <= sync_arst_n;
            sync_arst_n <= arst_n;
...
functional details 
[stdout]
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released before the extra delay window started.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260426_175047_007550_9b8266__sample_3
generated.v preview 
module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

reg srst_n_reg;
reg [1:0] delay_counter;
reg init_pulse_reg;

assign srst_n = srst_n_reg;
assign init_pulse = init_pulse_reg;

reg arst_n_sync1, arst_n_sync2;
reg srst_n_sync1, srst_n_sync2;

always @(posedge clk) begin
    arst_n_sync1 <= arst_n;
    arst_n_sync2 <= arst_n_sync1;
    srst_n_sync1 <= srst_n_reg;
    srst_n_sync2 <= srst_n_sync1;
end

always @(posedge clk) begin
    if (!arst_n) begin
        srst_n_reg <= 0;
        delay_counter <= 0;
        init_pulse_reg <= 0;
    end else if (srst_n_sync2 == 1'b0 && srst_n_sync1 == 1'b1) begin
        if (delay_counter < release_delay) begin
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260426_175047_007550_9b8266__sample_4
generated.v preview 
module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

reg srst_n_reg;
reg [1:0] delay_counter;
reg init_pulse_reg;

assign srst_n = srst_n_reg;
assign init_pulse = init_pulse_reg;

reg arst_n_sync1, arst_n_sync2;
reg srst_n_sync1, srst_n_sync2;

always @(posedge clk) begin
    arst_n_sync1 <= arst_n;
    arst_n_sync2 <= arst_n_sync1;
    srst_n_sync1 <= srst_n_reg;
    srst_n_sync2 <= srst_n_sync1;
end

always @(posedge clk) begin
    if (!arst_n) begin
        srst_n_reg <= 0;
        delay_counter <= 0;
        init_pulse_reg <= 0;
    end else if (srst_n_sync2 == 1'b0 && srst_n_sync1 == 1'b1) begin
        if (delay_counter < release_delay) begin
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset did not release with a one-cycle init pulse after the full delay.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260426_175047_007550_9b8266__sample_5
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg srst_n_reg;
    reg init_pulse_reg;
    reg [1:0] delay_counter;
    reg sync_arst_n;
    reg sync_arst_n_d1;
    reg reset_release_ready;
    reg reset_release_requested;

    assign srst_n = srst_n_reg;
    assign init_pulse = init_pulse_reg;

    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            srst_n_reg <= 0;
            init_pulse_reg <= 0;
            delay_counter <= 0;
            sync_arst_n <= 0;
            sync_arst_n_d1 <= 0;
            reset_release_ready <= 0;
            reset_release_requested <= 0;
        end else begin
            sync_arst_n_d1 <= sync_arst_n;
            sync_arst_n <= arst_n;
...
functional details 
[stdout]
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset did not release with a one-cycle init pulse after the full delay.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260426_175047_007550_9b8266__sample_6
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

reg srst_n_reg;
reg [1:0] delay_counter;
reg init_pulse_reg;

assign srst_n = srst_n_reg;
assign init_pulse = init_pulse_reg;

reg arst_n_sync1, arst_n_sync2;
reg srst_n_sync1, srst_n_sync2;

always @(posedge clk) begin
    arst_n_sync1 <= arst_n;
    arst_n_sync2 <= arst_n_sync1;
    srst_n_sync1 <= srst_n_reg;
    srst_n_sync2 <= srst_n_sync1;
end

always @(posedge clk) begin
    if (arst_n == 1'b0) begin
        srst_n_reg <= 1'b0;
        init_pulse_reg <= 1'b0;
    end else if (srst_n_sync2 == 1'b0 && srst_n_sync1 == 1'b1) begin
        if (delay_counter != 0) begin
            delay_counter <= delay_counter - 1;
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset did not release with a one-cycle init pulse after the full delay.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260426_175047_007550_9b8266__sample_7
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg srst_n_reg;
    reg init_pulse_reg;
    reg [1:0] delay_counter;
    reg sync_arst_n;
    reg sync_arst_n_d1;
    reg reset_release_ready;
    reg reset_release_requested;

    assign srst_n = srst_n_reg;
    assign init_pulse = init_pulse_reg;

    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            srst_n_reg <= 0;
            init_pulse_reg <= 0;
            delay_counter <= 0;
            sync_arst_n <= 0;
            sync_arst_n_d1 <= 0;
            reset_release_ready <= 0;
            reset_release_requested <= 0;
        end else begin
            sync_arst_n_d1 <= sync_arst_n;
            sync_arst_n <= arst_n;
...
functional details 
[stdout]
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset did not release with a one-cycle init pulse after the full delay.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260426_175047_007550_9b8266__sample_8
generated.v preview 
module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

reg srst_n_reg;
reg [1:0] delay_counter;
reg init_pulse_reg;

assign srst_n = srst_n_reg;
assign init_pulse = init_pulse_reg;

reg arst_n_sync1, arst_n_sync2;
reg srst_n_sync1, srst_n_sync2;

always @(posedge clk) begin
    arst_n_sync1 <= arst_n;
    arst_n_sync2 <= arst_n_sync1;
    srst_n_sync1 <= srst_n_reg;
    srst_n_sync2 <= srst_n_sync1;
end

always @(posedge clk) begin
    if (!arst_n) begin
        srst_n_reg <= 0;
        delay_counter <= 0;
        init_pulse_reg <= 0;
    end else if (srst_n_sync2 == 1'b0 && srst_n_sync1 == 1'b1) begin
        if (delay_counter < release_delay) begin
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset released before the extra delay window started.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260426_175047_007550_9b8266__sample_9
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg srst_n_reg;
    reg init_pulse_reg;
    reg [1:0] delay_counter;
    reg sync_arst_n;
    reg sync_arst_n_d1;
    reg reset_release_ready;
    reg reset_release_requested;

    assign srst_n = srst_n_reg;
    assign init_pulse = init_pulse_reg;

    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            srst_n_reg <= 0;
            init_pulse_reg <= 0;
            delay_counter <= 0;
            sync_arst_n <= 0;
            sync_arst_n_d1 <= 0;
            reset_release_ready <= 0;
            reset_release_requested <= 0;
        end else begin
            sync_arst_n_d1 <= sync_arst_n;
            sync_arst_n <= arst_n;
...
functional details 
[stdout]
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released before the extra delay window started.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260426_175047_007550_9b8266__sample_10
generated.v preview 
module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

reg srst_n_reg;
reg [1:0] delay_counter;
reg init_pulse_reg;

assign srst_n = srst_n_reg;
assign init_pulse = init_pulse_reg;

reg arst_n_sync1, arst_n_sync2;
reg srst_n_sync1, srst_n_sync2;

always @(posedge clk) begin
    arst_n_sync1 <= arst_n;
    arst_n_sync2 <= arst_n_sync1;
    srst_n_sync1 <= srst_n_reg;
    srst_n_sync2 <= srst_n_sync1;
end

always @(posedge clk) begin
    if (!arst_n) begin
        srst_n_reg <= 0;
        delay_counter <= 0;
        init_pulse_reg <= 0;
    end else if (srst_n_sync2 == 1'b0 && srst_n_sync1 == 1'b1) begin
        if (delay_counter < release_delay) begin
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}