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qwen3-coder:30b | RAG off

07_csr_register_map_generation / task_71 | apb_lock_cfg

benchmarkilyasov
task_idilyasov/07_csr_register_map_generation/task_71
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260426_175047_007550_9b8266

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260426_175047_007550_9b8266__sample_1
generated.v preview 
module apb_lock_cfg (
  input clk,
  input rst_n,
  input psel,
  input penable,
  input pwrite,
  input [7:0] paddr,
  input [31:0] pwdata,
  input [3:0] pstrb,
  output [31:0] prdata,
  output pready,
  input hw_fault_evt,
  output [1:0] mode,
  output [7:0] limit,
  output cfg_locked,
  output fault_sticky,
  output apply_pulse
);

  reg [1:0] mode_r;
  reg [7:0] limit_r;
  reg cfg_locked_r;
  reg fault_sticky_r;
  reg apply_pulse_r;

  assign mode = mode_r;
  assign limit = limit_r;
  assign cfg_locked = cfg_locked_r;
  assign fault_sticky = fault_sticky_r;
  assign apply_pulse = apply_pulse_r;

  reg pready_r;
...
functional details 
[stdout]
ERROR: CFG partial writes failed.
ERROR: CFG changed even though cfg_locked was asserted.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260426_175047_007550_9b8266__sample_2
generated.v preview 
module apb_lock_cfg (
  input        clk,
  input        rst_n,
  input        psel,
  input        penable,
  input        pwrite,
  input  [7:0] paddr,
  input  [31:0] pwdata,
  input  [3:0] pstrb,
  output [31:0] prdata,
  output       pready,
  input        hw_fault_evt,
  output [1:0] mode,
  output [7:0] limit,
  output       cfg_locked,
  output       fault_sticky,
  output       apply_pulse
);

  reg [1:0] mode_r;
  reg [7:0] limit_r;
  reg       cfg_locked_r;
  reg       fault_sticky_r;
  reg       apply_r;

  assign mode = mode_r;
  assign limit = limit_r;
  assign cfg_locked = cfg_locked_r;
  assign fault_sticky = fault_sticky_r;
  assign apply_pulse = apply_r;

  always @(posedge clk or negedge rst_n) begin
...
functional details 
[stdout]
ERROR: CFG partial writes failed.
ERROR: CFG changed even though cfg_locked was asserted.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_175047_007550_9b8266 ok failed failed skipped failed syntax /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/generated.v:84: error: apply_pulse_out is not a valid l-value in apb_lock_cfg.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260426_175047_007550_9b8266__sample_3
generated.v preview 
module apb_lock_cfg (
  input        clk,
  input        rst_n,
  input        psel,
  input        penable,
  input        pwrite,
  input  [7:0] paddr,
  input  [31:0] pwdata,
  input  [3:0] pstrb,
  output [31:0] prdata,
  output       pready,
  input        hw_fault_evt,
  output [1:0] mode,
  output [7:0] limit,
  output       cfg_locked,
  output       fault_sticky,
  output       apply_pulse
);

  reg [1:0] mode_reg;
  reg [7:0] limit_reg;
  reg       cfg_locked_reg;
  reg       fault_sticky_reg;
  reg       apply_reg;

  wire      apply_pulse_out;

  assign mode = mode_reg;
  assign limit = limit_reg;
  assign cfg_locked = cfg_locked_reg;
  assign fault_sticky = fault_sticky_reg;
  assign apply_pulse = apply_pulse_out;
...
syntax details 
[stderr]
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/generated.v:84: error: apply_pulse_out is not a valid l-value in apb_lock_cfg.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/generated.v:26:      : apply_pulse_out is declared here as wire.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/generated.v:86: error: apply_pulse_out is not a valid l-value in apb_lock_cfg.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/generated.v:26:      : apply_pulse_out is declared here as wire.
2 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/functional/generated.v:84: error: apply_pulse_out is not a valid l-value in tb_task_71.dut.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/functional/generated.v:26:      : apply_pulse_out is declared here as wire.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/functional/generated.v:86: error: apply_pulse_out is not a valid l-value in tb_task_71.dut.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/functional/generated.v:26:      : apply_pulse_out is declared here as wire.
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/generated.v:84: error: apply_pulse_out is not a valid l-value in apb_lock_cfg.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/generated.v:26:      : apply_pulse_out is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/generated.v:86: error: apply_pulse_out is not a valid l-value in apb_lock_cfg.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/generated.v:26:      : apply_pulse_out is declared here as wire.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/functional/generated.v:84: error: apply_pulse_out is not a valid l-value in tb_task_71.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/functional/generated.v:26:      : apply_pulse_out is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/functional/generated.v:86: error: apply_pulse_out is not a valid l-value in tb_task_71.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_3/functional/generated.v:26:      : apply_pulse_out is declared here as wire.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260426_175047_007550_9b8266__sample_4
generated.v preview 
module apb_lock_cfg (
  input clk,
  input rst_n,
  input psel,
  input penable,
  input pwrite,
  input [7:0] paddr,
  input [31:0] pwdata,
  input [3:0] pstrb,
  output [31:0] prdata,
  output pready,
  input hw_fault_evt,
  output [1:0] mode,
  output [7:0] limit,
  output cfg_locked,
  output fault_sticky,
  output apply_pulse
);

  reg [1:0] mode_r;
  reg [7:0] limit_r;
  reg cfg_locked_r;
  reg fault_sticky_r;
  reg apply_pulse_r;

  assign mode = mode_r;
  assign limit = limit_r;
  assign cfg_locked = cfg_locked_r;
  assign fault_sticky = fault_sticky_r;
  assign apply_pulse = apply_pulse_r;

  reg pready_r;
...
functional details 
[stdout]
ERROR: CFG partial writes failed.
ERROR: CFG changed even though cfg_locked was asserted.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_175047_007550_9b8266 ok failed failed skipped failed syntax _71/sample_5/generated.v:10: : prdata is declared here as wire.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260426_175047_007550_9b8266__sample_5
generated.v preview 
module apb_lock_cfg (
  input clk,
  input rst_n,
  input psel,
  input penable,
  input pwrite,
  input [7:0] paddr,
  input [31:0] pwdata,
  input [3:0] pstrb,
  output [31:0] prdata,
  output pready,
  input hw_fault_evt,
  output [1:0] mode,
  output [7:0] limit,
  output cfg_locked,
  output fault_sticky,
  output apply_pulse
);

  reg [1:0] mode_r;
  reg [7:0] limit_r;
  reg cfg_locked_r;
  reg fault_sticky_r;
  reg apply_pulse_r;

  wire apply_w;
  wire lock_w;
  wire status_w;

  assign mode = mode_r;
  assign limit = limit_r;
  assign cfg_locked = cfg_locked_r;
...
syntax details 
[stderr]
_71/sample_5/generated.v:10:      : prdata is declared here as wire.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:81: error: prdata is not a valid l-value in apb_lock_cfg.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:10:      : prdata is declared here as wire.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:82: error: prdata is not a valid l-value in apb_lock_cfg.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:10:      : prdata is declared here as wire.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:83: error: prdata is not a valid l-value in apb_lock_cfg.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:10:      : prdata is declared here as wire.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:84: error: prdata is not a valid l-value in apb_lock_cfg.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:10:      : prdata is declared here as wire.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:85: error: prdata is not a valid l-value in apb_lock_cfg.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:10:      : prdata is declared here as wire.
6 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:78: error: prdata is not a valid l-value in tb_task_71.dut.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:10:      : prdata is declared here as wire.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:81: error: prdata is not a valid l-value in tb_task_71.dut.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:10:      : prdata is declared here as wire.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:82: error: prdata is not a valid l-value in tb_task_71.dut.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:10:      : prdata is declared here as wire.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:83: error: prdata is not a valid l-value in tb_task_71.dut.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:10:      : prdata is declared here as wire.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:84: error: prdata is not a valid l-value in tb_task_71.dut.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:10:      : prdata is declared here as wire.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:85: error: prdata is not a valid l-value in tb_task_71.dut.
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:10:      : prdata is declared here as wire.
6 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "_71/sample_5/generated.v:10:      : prdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:81: error: prdata is not a valid l-value in apb_lock_cfg.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:10:      : prdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:82: error: prdata is not a valid l-value in apb_lock_cfg.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:10:      : prdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:83: error: prdata is not a valid l-value in apb_lock_cfg.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:10:      : prdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:84: error: prdata is not a valid l-value in apb_lock_cfg.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:10:      : prdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:85: error: prdata is not a valid l-value in apb_lock_cfg.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/generated.v:10:      : prdata is declared here as wire.\n6 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:78: error: prdata is not a valid l-value in tb_task_71.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:10:      : prdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:81: error: prdata is not a valid l-value in tb_task_71.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:10:      : prdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:82: error: prdata is not a valid l-value in tb_task_71.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:10:      : prdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:83: error: prdata is not a valid l-value in tb_task_71.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:10:      : prdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:84: error: prdata is not a valid l-value in tb_task_71.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:10:      : prdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:85: error: prdata is not a valid l-value in tb_task_71.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_71/sample_5/functional/generated.v:10:      : prdata is declared here as wire.\n6 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260426_175047_007550_9b8266__sample_6
generated.v preview 
module apb_lock_cfg (
  input clk,
  input rst_n,
  input psel,
  input penable,
  input pwrite,
  input [7:0] paddr,
  input [31:0] pwdata,
  input [3:0] pstrb,
  output [31:0] prdata,
  output pready,
  input hw_fault_evt,
  output [1:0] mode,
  output [7:0] limit,
  output cfg_locked,
  output fault_sticky,
  output apply_pulse
);

  reg [1:0] mode_r;
  reg [7:0] limit_r;
  reg cfg_locked_r;
  reg fault_sticky_r;
  reg apply_pulse_r;

  assign mode = mode_r;
  assign limit = limit_r;
  assign cfg_locked = cfg_locked_r;
  assign fault_sticky = fault_sticky_r;
  assign apply_pulse = apply_pulse_r;

  reg pready_r;
...
functional details 
[stdout]
ERROR: CFG partial writes failed.
ERROR: CFG changed even though cfg_locked was asserted.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260426_175047_007550_9b8266__sample_7
generated.v preview 
module apb_lock_cfg (
  input clk,
  input rst_n,
  input psel,
  input penable,
  input pwrite,
  input [7:0] paddr,
  input [31:0] pwdata,
  input [3:0] pstrb,
  output [31:0] prdata,
  output pready,
  input hw_fault_evt,
  output [1:0] mode,
  output [7:0] limit,
  output cfg_locked,
  output fault_sticky,
  output apply_pulse
);

  reg [1:0] mode_r;
  reg [7:0] limit_r;
  reg cfg_locked_r;
  reg fault_sticky_r;
  reg apply_pulse_r;

  assign mode = mode_r;
  assign limit = limit_r;
  assign cfg_locked = cfg_locked_r;
  assign fault_sticky = fault_sticky_r;
  assign apply_pulse = apply_pulse_r;

  reg pready_r;
...
functional details 
[stdout]
ERROR: CFG partial writes failed.
ERROR: CFG changed even though cfg_locked was asserted.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260426_175047_007550_9b8266__sample_8
generated.v preview 
module apb_lock_cfg (
  input clk,
  input rst_n,
  input psel,
  input penable,
  input pwrite,
  input [7:0] paddr,
  input [31:0] pwdata,
  input [3:0] pstrb,
  output [31:0] prdata,
  output pready,
  input hw_fault_evt,
  output [1:0] mode,
  output [7:0] limit,
  output cfg_locked,
  output fault_sticky,
  output apply_pulse
);

  reg [1:0] mode_r;
  reg [7:0] limit_r;
  reg cfg_locked_r;
  reg fault_sticky_r;
  reg apply_pulse_r;

  wire apply_w;
  wire lock_w;
  wire status_w;
  wire cfg_w;

  assign mode = mode_r;
  assign limit = limit_r;
...
functional details 
[stdout]
ERROR: CFG partial writes failed.
ERROR: CFG changed even though cfg_locked was asserted.
ERROR: apply_pulse did not assert.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260426_175047_007550_9b8266__sample_9
generated.v preview 
module apb_lock_cfg (
  input clk,
  input rst_n,
  input psel,
  input penable,
  input pwrite,
  input [7:0] paddr,
  input [31:0] pwdata,
  input [3:0] pstrb,
  output [31:0] prdata,
  output pready,
  input hw_fault_evt,
  output [1:0] mode,
  output [7:0] limit,
  output cfg_locked,
  output fault_sticky,
  output apply_pulse
);

  reg [1:0] mode_r;
  reg [7:0] limit_r;
  reg cfg_locked_r;
  reg fault_sticky_r;
  reg apply_pulse_r;

  wire apply_w;
  wire lock_w;
  wire status_w;
  wire cfg_w;

  assign mode = mode_r;
  assign limit = limit_r;
...
functional details 
[stdout]
ERROR: CFG partial writes failed.
ERROR: CFG changed even though cfg_locked was asserted.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260426_175047_007550_9b8266__sample_10
generated.v preview 
module apb_lock_cfg (
  input clk,
  input rst_n,
  input psel,
  input penable,
  input pwrite,
  input [7:0] paddr,
  input [31:0] pwdata,
  input [3:0] pstrb,
  output [31:0] prdata,
  output pready,
  input hw_fault_evt,
  output [1:0] mode,
  output [7:0] limit,
  output cfg_locked,
  output fault_sticky,
  output apply_pulse
);

  reg [1:0] mode_r;
  reg [7:0] limit_r;
  reg cfg_locked_r;
  reg fault_sticky_r;
  reg apply_pulse_r;

  assign mode = mode_r;
  assign limit = limit_r;
  assign cfg_locked = cfg_locked_r;
  assign fault_sticky = fault_sticky_r;
  assign apply_pulse = apply_pulse_r;

  reg pready_r;
...
functional details 
[stdout]
ERROR: CFG partial writes failed.
ERROR: CFG changed even though cfg_locked was asserted.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}