07_csr_register_map_generation / task_72 | axil_sensor_csr
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260426_175047_007550_9b8266 | ok | failed | failed | skipped | failed | syntax | val/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:107: error: rdata is not a valid l-value in axil_sensor_csr. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_175047_007550_9b8266__sample_1
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output arready,
output [31:0] rdata,
output [1:0] rresp,
output rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output block_enable,
output [7:0] gain,
output kick_pulse,
output irq_sticky
);
// Register definitions
reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] cmd_reg;
...
syntax details[stderr] val/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:107: error: rdata is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:108: error: rdata is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:109: error: rdata is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:110: error: rdata is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:145: sorry: Assignment to an entire array or to an array slice is not yet supported. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:158: sorry: Assignment to an entire array or to an array slice is not yet supported. 6 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:107: error: rdata is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:108: error: rdata is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:109: error: rdata is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:110: error: rdata is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:145: sorry: Assignment to an entire array or to an array slice is not yet supported. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:158: sorry: Assignment to an entire array or to an array slice is not yet supported. 6 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "val/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:107: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:108: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:109: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:110: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:145: sorry: Assignment to an entire array or to an array slice is not yet supported.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:158: sorry: Assignment to an entire array or to an array slice is not yet supported.\n6 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:107: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:108: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:109: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:110: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:145: sorry: Assignment to an entire array or to an array slice is not yet supported.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:158: sorry: Assignment to an entire array or to an array slice is not yet supported.\n6 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260426_175047_007550_9b8266 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_175047_007550_9b8266__sample_2
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output arready,
output [31:0] rdata,
output [1:0] rresp,
output rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output block_enable,
output [7:0] gain,
output kick_pulse,
output irq_sticky
);
// Register definitions
reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] cmd_reg;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL gain field failed. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: STATUS read with IRQ bit set returned wrong value. Got 0000005c ERROR: AXI-Lite write response was not generated correctly. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite CMD write response was not generated correctly. ERROR: kick_pulse did not assert on CMD write. ERROR: CMD register should read as zero. Got 0001005c TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260426_175047_007550_9b8266 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_175047_007550_9b8266__sample_3
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output arready,
output [31:0] rdata,
output [1:0] rresp,
output rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output block_enable,
output [7:0] gain,
output kick_pulse,
output irq_sticky
);
// Register definitions
reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] cmd_reg;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL gain field failed. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000001 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: AXI-Lite CMD write response was not generated correctly. ERROR: kick_pulse did not assert on CMD write. ERROR: kick_pulse lasted longer than one cycle. TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260426_175047_007550_9b8266 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_175047_007550_9b8266__sample_4
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output arready,
output [31:0] rdata,
output [1:0] rresp,
output rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output block_enable,
output [7:0] gain,
output kick_pulse,
output irq_sticky
);
// Register definitions
reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] cmd_reg;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL gain field failed. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000000 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: AXI-Lite CMD write response was not generated correctly. ERROR: kick_pulse did not assert on CMD write. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260426_175047_007550_9b8266 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_175047_007550_9b8266__sample_5
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output arready,
output [31:0] rdata,
output [1:0] rresp,
output rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output block_enable,
output [7:0] gain,
output kick_pulse,
output irq_sticky
);
// Register definitions
reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] cmd_reg;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL gain field failed. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000100 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: kick_pulse did not assert on CMD write. ERROR: kick_pulse lasted longer than one cycle. TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260426_175047_007550_9b8266 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:191: error: arready is not a valid l-value in axil_sensor_csr. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_175047_007550_9b8266__sample_6
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output arready,
output [31:0] rdata,
output [1:0] rresp,
output rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output block_enable,
output [7:0] gain,
output kick_pulse,
output irq_sticky
);
// Register definitions
reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] cmd_reg;
...
syntax details[stderr] /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:191: error: arready is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:194: error: arready is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:196: error: arready is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:16: : arready is declared here as wire. 3 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:191: error: arready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:194: error: arready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:196: error: arready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:16: : arready is declared here as wire. 3 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:191: error: arready is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:194: error: arready is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:196: error: arready is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:16: : arready is declared here as wire.\n3 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:191: error: arready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:194: error: arready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:196: error: arready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:16: : arready is declared here as wire.\n3 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260426_175047_007550_9b8266 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_175047_007550_9b8266__sample_7
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output arready,
output [31:0] rdata,
output [1:0] rresp,
output rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output block_enable,
output [7:0] gain,
output kick_pulse,
output irq_sticky
);
// Register definitions
reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] cmd_reg;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL gain field failed. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000000 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: AXI-Lite CMD write response was not generated correctly. ERROR: kick_pulse did not assert on CMD write. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260426_175047_007550_9b8266 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_175047_007550_9b8266__sample_8
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output arready,
output [31:0] rdata,
output [1:0] rresp,
output rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output block_enable,
output [7:0] gain,
output kick_pulse,
output irq_sticky
);
// Register definitions
reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] cmd_reg;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL gain field failed. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read without IRQ bit set returned wrong value. Got 0000005c ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read with IRQ bit set returned wrong value. Got 0000805c ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: kick_pulse did not assert on CMD write. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260426_175047_007550_9b8266 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_175047_007550_9b8266__sample_9
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output arready,
output [31:0] rdata,
output [1:0] rresp,
output rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output block_enable,
output [7:0] gain,
output kick_pulse,
output irq_sticky
);
// Register definitions
reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] cmd_reg;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL gain field failed. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: STATUS read with IRQ bit set returned wrong value. Got 00005c00 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: AXI-Lite CMD write response was not generated correctly. ERROR: kick_pulse did not assert on CMD write. ERROR: CMD register should read as zero. Got 00005c00 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260426_175047_007550_9b8266 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_175047_007550_9b8266__sample_10
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output arready,
output [31:0] rdata,
output [1:0] rresp,
output rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output block_enable,
output [7:0] gain,
output kick_pulse,
output irq_sticky
);
// Register definitions
reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] cmd_reg;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: byte-lane write to CTRL gain field failed. ERROR: STATUS read with IRQ bit set returned wrong value. Got 00005c00 ERROR: W1C clear of irq_sticky failed. ERROR: kick_pulse did not assert on CMD write. ERROR: kick_pulse lasted longer than one cycle. TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|