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qwen3-coder:30b | RAG off

07_csr_register_map_generation / task_73 | apb_sample_csr

benchmarkilyasov
task_idilyasov/07_csr_register_map_generation/task_73
samples_total10
final_success_samples1
final_success_rate_samples10.0%
functional_pass_rate_samples10.0%
synth_pass_rate_samples10.0%
source_runsrun_20260426_175047_007550_9b8266

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_175047_007550_9b8266 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_73\samples\run_20260426_175047_007550_9b8266__sample_1
generated.v preview
module apb_sample_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input sample_push,
    input [7:0] sample_data,
    output [7:0] threshold,
    output irq_out,
    output ack_pulse
);

reg [31:0] reg_config;
reg [31:0] reg_status;
reg [31:0] reg_data;
reg [31:0] reg_cmd;
reg [7:0] latched_sample;
reg data_pending;
reg ack_pulse_reg;

assign threshold = reg_config[7:0];
assign irq_out = data_pending;
assign ack_pulse = ack_pulse_reg;

reg apb_write;
reg apb_read;
...
syntax details
[stderr]
/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/pashencev__07_csr_register_map_generation__task_73/sample_1/generated.v:80: warning: Extra digits given for sized hex constant.
functional details
[stdout]
TEST_PASSED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_73/tb.v:178: $finish called at 156000 (1ps)
synthesis details
[error]
None
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_2 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: threshold write failed.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_73\samples\run_20260426_175047_007550_9b8266__sample_2
generated.v preview
module apb_sample_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input sample_push,
    input [7:0] sample_data,
    output reg [7:0] threshold,
    output reg irq_out,
    output reg ack_pulse
);

reg [31:0] config_reg;
reg [31:0] status_reg;
reg [31:0] data_reg;
reg [31:0] cmd_reg;

reg data_pending;
reg sample_latched;
reg [7:0] latched_sample;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        config_reg <= 32'h00000020;
        status_reg <= 32'h00000000;
        data_reg <= 32'h00000000;
...
functional details
[stdout]
ERROR: threshold write failed.
ERROR: sample_push did not set data_pending.
ERROR: STATUS readback failed. Got 00000000
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_73/tb.v:178: $finish called at 156000 (1ps)
synthesis details
[error]
None
errors[]
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: threshold write failed.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: threshold write failed.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_73\samples\run_20260426_175047_007550_9b8266__sample_3
generated.v preview
module apb_sample_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input sample_push,
    input [7:0] sample_data,
    output reg [7:0] threshold,
    output reg irq_out,
    output reg ack_pulse
);

reg [31:0] config_reg;
reg [31:0] status_reg;
reg [31:0] data_reg;
reg [31:0] cmd_reg;
reg data_pending;
reg sample_latched;
reg [7:0] latched_sample;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        config_reg <= 32'h00000020;
        status_reg <= 32'h00000000;
        data_reg <= 32'h00000000;
        cmd_reg <= 32'h00000000;
...
functional details
[stdout]
ERROR: threshold write failed.
ERROR: STATUS readback failed. Got 00000000
ERROR: DATA read did not clear data_pending.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_73/tb.v:178: $finish called at 156000 (1ps)
synthesis details
[error]
None
errors[]
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: threshold write failed.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: STATUS readback failed. Got 00000000
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_73\samples\run_20260426_175047_007550_9b8266__sample_4
generated.v preview
module apb_sample_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input sample_push,
    input [7:0] sample_data,
    output reg [7:0] threshold,
    output reg irq_out,
    output reg ack_pulse
);

reg [31:0] config_reg;
reg [31:0] status_reg;
reg [31:0] data_reg;
reg [31:0] cmd_reg;

reg data_pending;
reg sample_latched;
reg [7:0] latched_sample;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        config_reg <= 32'h00000020;
        status_reg <= 32'h00000000;
        data_reg <= 32'h00000000;
...
functional details
[stdout]
ERROR: STATUS readback failed. Got 00000000
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_73/tb.v:178: $finish called at 156000 (1ps)
synthesis details
[error]
None
errors[]
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: STATUS readback failed. Got 00000000",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: threshold write failed.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_73\samples\run_20260426_175047_007550_9b8266__sample_5
generated.v preview
module apb_sample_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input sample_push,
    input [7:0] sample_data,
    output reg [7:0] threshold,
    output reg irq_out,
    output reg ack_pulse
);

reg [31:0] config_reg;
reg [31:0] status_reg;
reg [31:0] data_reg;
reg [31:0] cmd_reg;

reg data_pending;
reg sample_latched;
reg [7:0] latched_sample;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        config_reg <= 32'h00000020;
        status_reg <= 32'h00000000;
        data_reg <= 32'h00000000;
...
functional details
[stdout]
ERROR: threshold write failed.
ERROR: sample_push did not set data_pending.
ERROR: STATUS readback failed. Got 00000000
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_73/tb.v:178: $finish called at 156000 (1ps)
synthesis details
[error]
None
errors[]
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: threshold write failed.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: STATUS readback failed. Got 00000000
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_73\samples\run_20260426_175047_007550_9b8266__sample_6
generated.v preview
module apb_sample_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input sample_push,
    input [7:0] sample_data,
    output reg [7:0] threshold,
    output reg irq_out,
    output reg ack_pulse
);

reg [31:0] config_reg;
reg [31:0] status_reg;
reg [31:0] data_reg;
reg [31:0] cmd_reg;

reg data_pending;
reg sample_latched;
reg [7:0] latched_sample;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        config_reg <= 32'h00000020;
        status_reg <= 32'h00000000;
        data_reg <= 32'h00000000;
...
functional details
[stdout]
ERROR: STATUS readback failed. Got 00000000
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_73/tb.v:178: $finish called at 156000 (1ps)
synthesis details
[error]
None
errors[]
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: STATUS readback failed. Got 00000000",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: threshold write failed.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_73\samples\run_20260426_175047_007550_9b8266__sample_7
generated.v preview
module apb_sample_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input sample_push,
    input [7:0] sample_data,
    output reg [7:0] threshold,
    output reg irq_out,
    output reg ack_pulse
);

reg [31:0] config_reg;
reg [31:0] status_reg;
reg [31:0] data_reg;
reg [31:0] cmd_reg;
reg data_pending;
reg sample_latched;
reg [7:0] latched_sample;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        config_reg <= 32'h00000020;
        status_reg <= 32'h00000000;
        data_reg <= 32'h00000000;
        cmd_reg <= 32'h00000000;
...
functional details
[stdout]
ERROR: threshold write failed.
ERROR: STATUS readback failed. Got 00000000
ERROR: DATA read did not clear data_pending.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_73/tb.v:178: $finish called at 156000 (1ps)
synthesis details
[error]
None
errors[]
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: threshold write failed.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: STATUS readback failed. Got 00000000
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_73\samples\run_20260426_175047_007550_9b8266__sample_8
generated.v preview
module apb_sample_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input sample_push,
    input [7:0] sample_data,
    output reg [7:0] threshold,
    output reg irq_out,
    output reg ack_pulse
);

reg [31:0] config_reg;
reg [31:0] status_reg;
reg [31:0] data_reg;
reg [31:0] cmd_reg;

reg data_pending;
reg sample_latched;
reg [7:0] latched_sample;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        config_reg <= 32'h00000020;
        status_reg <= 32'h00000000;
        data_reg <= 32'h00000000;
...
functional details
[stdout]
ERROR: STATUS readback failed. Got 00000000
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_73/tb.v:178: $finish called at 156000 (1ps)
synthesis details
[error]
None
errors[]
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: STATUS readback failed. Got 00000000",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: sample_push did not set data_pending.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_73\samples\run_20260426_175047_007550_9b8266__sample_9
generated.v preview
module apb_sample_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input sample_push,
    input [7:0] sample_data,
    output reg [7:0] threshold,
    output reg irq_out,
    output reg ack_pulse
);

reg [31:0] config_reg;
reg [31:0] status_reg;
reg [31:0] data_reg;
reg [31:0] cmd_reg;

reg data_pending;
reg sample_latched;
reg [7:0] latched_sample;

reg write_en;
reg [31:0] write_data;
reg [3:0] write_strobe;

always @(posedge clk or negedge rst_n) begin
...
functional details
[stdout]
ERROR: sample_push did not set data_pending.
ERROR: STATUS readback failed. Got 00000000
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_73/tb.v:178: $finish called at 156000 (1ps)
synthesis details
[error]
None
errors[]
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: sample_push did not set data_pending.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: threshold write failed.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_73\samples\run_20260426_175047_007550_9b8266__sample_10
generated.v preview
module apb_sample_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input sample_push,
    input [7:0] sample_data,
    output reg [7:0] threshold,
    output reg irq_out,
    output reg ack_pulse
);

reg [31:0] config_reg;
reg [31:0] status_reg;
reg [31:0] data_reg;
reg [31:0] cmd_reg;

reg data_pending;
reg sample_latched;
reg [7:0] latched_sample;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        config_reg <= 32'h00000020;
        status_reg <= 32'h00000000;
        data_reg <= 32'h00000000;
...
functional details
[stdout]
ERROR: threshold write failed.
ERROR: sample_push did not set data_pending.
ERROR: STATUS readback failed. Got 00000000
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_73/tb.v:178: $finish called at 156000 (1ps)
synthesis details
[error]
None
errors[]
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: threshold write failed.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}