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qwen3-coder:30b | RAG off

12_cdv / task_121 | queue_credit_tracker

benchmarkilyasov
task_idilyasov/12_cdv/task_121
samples_total10
final_success_samples3
final_success_rate_samples30.0%
functional_pass_rate_samples100.0%
synth_pass_rate_samples30.0%
source_runsrun_20260426_175047_007550_9b8266

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_175047_007550_9b8266 ok ok n/a ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260426_175047_007550_9b8266__sample_1
generated.v preview 
module queue_credit_tracker (
    input wire clk,
    input wire rst_n,
    input wire push,
    input wire pop,
    input wire flush,
    input wire [1:0] cfg_limit,
    output wire overflow_pulse,
    output wire underflow_pulse,
    output wire [2:0] count
);

reg [2:0] count_reg;
reg overflow_pulse_reg;
reg underflow_pulse_reg;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count_reg <= 3'b000;
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
    end else begin
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
        
        if (flush) begin
            count_reg <= 3'b000;
        end else if (push && !pop) begin
            if (count_reg < cfg_limit + 1) begin
                count_reg <= count_reg + 1;
            end else begin
                overflow_pulse_reg <= 1'b1;
...
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": false,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_2 run_20260426_175047_007550_9b8266 ok ok n/a ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260426_175047_007550_9b8266__sample_2
generated.v preview 
module queue_credit_tracker (
    input wire clk,
    input wire rst_n,
    input wire push,
    input wire pop,
    input wire flush,
    input wire [1:0] cfg_limit,
    output wire overflow_pulse,
    output wire underflow_pulse,
    output wire [2:0] count
);

reg [2:0] count_reg;
reg overflow_pulse_reg;
reg underflow_pulse_reg;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count_reg <= 3'b000;
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
    end else begin
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
        
        if (flush) begin
            count_reg <= 3'b000;
        end else if (push && !pop) begin
            if (count_reg < cfg_limit + 1) begin
                count_reg <= count_reg + 1;
            end else begin
                overflow_pulse_reg <= 1'b1;
...
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": false,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_3 run_20260426_175047_007550_9b8266 ok ok n/a ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260426_175047_007550_9b8266__sample_3
generated.v preview 
module queue_credit_tracker (
    input wire clk,
    input wire rst_n,
    input wire push,
    input wire pop,
    input wire flush,
    input wire [1:0] cfg_limit,
    output wire overflow_pulse,
    output wire underflow_pulse,
    output wire [2:0] count
);

reg [2:0] count_reg;
reg overflow_pulse_reg;
reg underflow_pulse_reg;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count_reg <= 3'b000;
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
    end else begin
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
        
        if (flush) begin
            count_reg <= 3'b000;
        end else if (push && !pop) begin
            if (count_reg < cfg_limit + 1) begin
                count_reg <= count_reg + 1;
            end else begin
                overflow_pulse_reg <= 1'b1;
...
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": false,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_4 run_20260426_175047_007550_9b8266 ok ok n/a failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260426_175047_007550_9b8266__sample_4
generated.v preview 
module queue_credit_tracker (
    input wire clk,
    input wire rst_n,
    input wire push,
    input wire pop,
    input wire flush,
    input wire [1:0] cfg_limit,
    output wire overflow_pulse,
    output wire underflow_pulse,
    output wire [2:0] count
);

reg [2:0] count_reg;
reg overflow_pulse_reg;
reg underflow_pulse_reg;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count_reg <= 3'b000;
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
    end else begin
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
        
        if (flush) begin
            count_reg <= 3'b000;
        end else if (push && !pop) begin
            if (count_reg < cfg_limit + 1) begin
                count_reg <= count_reg + 1;
            end else begin
                overflow_pulse_reg <= 1'b1;
...
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": false,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_175047_007550_9b8266 ok ok n/a failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260426_175047_007550_9b8266__sample_5
generated.v preview 
module queue_credit_tracker (
    input wire clk,
    input wire rst_n,
    input wire push,
    input wire pop,
    input wire flush,
    input wire [1:0] cfg_limit,
    output wire overflow_pulse,
    output wire underflow_pulse,
    output wire [2:0] count
);

reg [2:0] count_reg;
reg overflow_pulse_reg;
reg underflow_pulse_reg;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count_reg <= 3'b000;
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
    end else begin
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
        
        if (flush) begin
            count_reg <= 3'b000;
        end else if (push && !pop) begin
            if (count_reg < cfg_limit + 1) begin
                count_reg <= count_reg + 1;
            end else begin
                overflow_pulse_reg <= 1'b1;
...
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": false,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_175047_007550_9b8266 ok ok n/a failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260426_175047_007550_9b8266__sample_6
generated.v preview 
module queue_credit_tracker (
    input wire clk,
    input wire rst_n,
    input wire push,
    input wire pop,
    input wire flush,
    input wire [1:0] cfg_limit,
    output wire overflow_pulse,
    output wire underflow_pulse,
    output wire [2:0] count
);

reg [2:0] count_reg;
reg overflow_pulse_reg;
reg underflow_pulse_reg;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count_reg <= 3'b000;
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
    end else begin
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
        
        if (flush) begin
            count_reg <= 3'b000;
        end else if (push && !pop) begin
            if (count_reg < cfg_limit + 1) begin
                count_reg <= count_reg + 1;
            end else begin
                overflow_pulse_reg <= 1'b1;
...
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": false,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_175047_007550_9b8266 ok ok n/a failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260426_175047_007550_9b8266__sample_7
generated.v preview 
module queue_credit_tracker (
    input wire clk,
    input wire rst_n,
    input wire push,
    input wire pop,
    input wire flush,
    input wire [1:0] cfg_limit,
    output wire overflow_pulse,
    output wire underflow_pulse,
    output wire [2:0] count
);

reg [2:0] count_reg;
reg overflow_pulse_reg;
reg underflow_pulse_reg;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count_reg <= 3'b000;
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
    end else begin
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
        
        if (flush) begin
            count_reg <= 3'b000;
        end else if (push && !pop) begin
            if (count_reg < cfg_limit + 1) begin
                count_reg <= count_reg + 1;
            end else begin
                overflow_pulse_reg <= 1'b1;
...
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": false,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_175047_007550_9b8266 ok ok n/a failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260426_175047_007550_9b8266__sample_8
generated.v preview 
module queue_credit_tracker (
    input wire clk,
    input wire rst_n,
    input wire push,
    input wire pop,
    input wire flush,
    input wire [1:0] cfg_limit,
    output wire overflow_pulse,
    output wire underflow_pulse,
    output wire [2:0] count
);

reg [2:0] count_reg;
reg overflow_pulse_reg;
reg underflow_pulse_reg;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count_reg <= 3'b000;
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
    end else begin
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
        
        if (flush) begin
            count_reg <= 3'b000;
        end else if (push && !pop) begin
            if (count_reg < cfg_limit + 1) begin
                count_reg <= count_reg + 1;
            end else begin
                overflow_pulse_reg <= 1'b1;
...
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": false,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_175047_007550_9b8266 ok ok n/a failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260426_175047_007550_9b8266__sample_9
generated.v preview 
module queue_credit_tracker (
    input wire clk,
    input wire rst_n,
    input wire push,
    input wire pop,
    input wire flush,
    input wire [1:0] cfg_limit,
    output wire overflow_pulse,
    output wire underflow_pulse,
    output wire [2:0] count
);

reg [2:0] count_reg;
reg overflow_pulse_reg;
reg underflow_pulse_reg;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count_reg <= 3'b000;
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
    end else begin
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
        
        if (flush) begin
            count_reg <= 3'b000;
        end else if (push && !pop) begin
            if (count_reg < cfg_limit + 1) begin
                count_reg <= count_reg + 1;
            end else begin
                overflow_pulse_reg <= 1'b1;
...
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": false,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_175047_007550_9b8266 ok ok n/a failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260426_175047_007550_9b8266__sample_10
generated.v preview 
module queue_credit_tracker (
    input wire clk,
    input wire rst_n,
    input wire push,
    input wire pop,
    input wire flush,
    input wire [1:0] cfg_limit,
    output wire overflow_pulse,
    output wire underflow_pulse,
    output wire [2:0] count
);

reg [2:0] count_reg;
reg overflow_pulse_reg;
reg underflow_pulse_reg;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count_reg <= 3'b000;
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
    end else begin
        overflow_pulse_reg <= 1'b0;
        underflow_pulse_reg <= 1'b0;
        
        if (flush) begin
            count_reg <= 3'b000;
        end else if (push && !pop) begin
            if (count_reg < cfg_limit + 1) begin
                count_reg <= count_reg + 1;
            end else begin
                overflow_pulse_reg <= 1'b1;
...
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": false,
  "openlane_required": true,
  "final_success": false,
  "success": false
}