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qwen3-coder:30b | RAG off

13_rtllm_arithmetic / task_02 | verified_adder_16bit

benchmarkrtllm
task_idrtllm/13_rtllm_arithmetic/task_02
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples100.0%
synth_pass_rate_samples0.0%
source_runsrun_20260426_175047_007550_9b8266

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_175047_007550_9b8266 ok ok ok failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_175047_007550_9b8266__sample_1
generated.v preview 
module adder_16bit(
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [7:0] sum_low;
    wire [7:0] sum_high;
    wire c1, c2, c3;

    // Instantiate two 8-bit adders
    adder_8bit u_low (
        .a(a[7:0]),
        .b(b[7:0]),
        .Cin(Cin),
        .y(sum_low),
        .Co(c1)
    );

    adder_8bit u_high (
        .a(a[15:8]),
        .b(b[15:8]),
        .Cin(c1),
        .y(sum_high),
        .Co(c2)
    );

    // Combine results
    assign y = {sum_high, sum_low};
    assign Co = c2;
...
functional details 
[stdout]
===========Test completed with          43 / 100 failures===========
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_175047_007550_9b8266 ok ok ok failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_175047_007550_9b8266__sample_2
generated.v preview 
module adder_16bit(
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [7:0] sum_low;
    wire [7:0] sum_high;
    wire carry_8;
    wire carry_16;

    // Instantiate two 8-bit adders
    adder_8bit u_adder_low (
        .a      (a[7:0]),
        .b      (b[7:0]),
        .Cin    (Cin),
        .y      (sum_low),
        .Co     (carry_8)
    );

    adder_8bit u_adder_high (
        .a      (a[15:8]),
        .b      (b[15:8]),
        .Cin    (carry_8),
        .y      (sum_high),
        .Co     (carry_16)
    );

    // Combine results
    assign y = {sum_high, sum_low};
...
functional details 
[stdout]
===========Test completed with          43 / 100 failures===========
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_175047_007550_9b8266 ok ok ok failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_175047_007550_9b8266__sample_3
generated.v preview 
module adder_16bit(
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [7:0] sum_low;
    wire [7:0] sum_high;
    wire c1, c2, c3;

    // Instantiate two 8-bit adders
    adder_8bit u_adder_low (
        .a(a[7:0]),
        .b(b[7:0]),
        .Cin(Cin),
        .y(sum_low),
        .Co(c1)
    );

    adder_8bit u_adder_high (
        .a(a[15:8]),
        .b(b[15:8]),
        .Cin(c1),
        .y(sum_high),
        .Co(c2)
    );

    // Combine results
    assign y = {sum_high, sum_low};
    assign Co = c2;
...
functional details 
[stdout]
===========Test completed with          43 / 100 failures===========
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_175047_007550_9b8266 ok ok ok failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_175047_007550_9b8266__sample_4
generated.v preview 
module adder_16bit(
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [7:0] sum_low;
    wire [7:0] sum_high;
    wire c1, c2, c3;

    // Instantiate two 8-bit adders
    adder_8bit u_adder_low (
        .a(a[7:0]),
        .b(b[7:0]),
        .Cin(Cin),
        .y(sum_low),
        .Co(c1)
    );

    adder_8bit u_adder_high (
        .a(a[15:8]),
        .b(b[15:8]),
        .Cin(c1),
        .y(sum_high),
        .Co(c2)
    );

    // Combine outputs
    assign y = {sum_high, sum_low};
    assign Co = c2;
...
functional details 
[stdout]
===========Test completed with          43 / 100 failures===========
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_175047_007550_9b8266 ok ok ok failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_175047_007550_9b8266__sample_5
generated.v preview 
module adder_16bit(
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [7:0] sum_low;
    wire [7:0] sum_high;
    wire c1, c2, c3;

    // Instantiate two 8-bit adders
    adder_8bit u_adder_low (
        .a(a[7:0]),
        .b(b[7:0]),
        .Cin(Cin),
        .y(sum_low),
        .Co(c1)
    );

    adder_8bit u_adder_high (
        .a(a[15:8]),
        .b(b[15:8]),
        .Cin(c1),
        .y(sum_high),
        .Co(c2)
    );

    // Combine outputs
    assign y = {sum_high, sum_low};
    assign Co = c2;
...
functional details 
[stdout]
===========Test completed with          43 / 100 failures===========
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_175047_007550_9b8266 ok ok ok failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_175047_007550_9b8266__sample_6
generated.v preview 
module adder_16bit(
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [7:0] sum_low;
    wire [7:0] sum_high;
    wire c1, c2, c3;

    // Instantiate two 8-bit adders
    adder_8bit u_adder_low (
        .a(a[7:0]),
        .b(b[7:0]),
        .Cin(Cin),
        .y(sum_low),
        .Co(c1)
    );

    adder_8bit u_adder_high (
        .a(a[15:8]),
        .b(b[15:8]),
        .Cin(c1),
        .y(sum_high),
        .Co(c2)
    );

    // Combine results
    assign y = {sum_high, sum_low};
    assign Co = c2;
...
functional details 
[stdout]
===========Test completed with          43 / 100 failures===========
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_175047_007550_9b8266 ok ok ok failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_175047_007550_9b8266__sample_7
generated.v preview 
module adder_16bit(
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [7:0] sum_low;
    wire [7:0] sum_high;
    wire carry_8;
    wire carry_16;

    // Instantiate two 8-bit adders
    adder_8bit u_adder_low (
        .a      (a[7:0]),
        .b      (b[7:0]),
        .Cin    (Cin),
        .y      (sum_low),
        .Co     (carry_8)
    );

    adder_8bit u_adder_high (
        .a      (a[15:8]),
        .b      (b[15:8]),
        .Cin    (carry_8),
        .y      (sum_high),
        .Co     (carry_16)
    );

    // Combine outputs
    assign y = {sum_high, sum_low};
...
functional details 
[stdout]
===========Test completed with          43 / 100 failures===========
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_175047_007550_9b8266 ok ok ok failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_175047_007550_9b8266__sample_8
generated.v preview 
module adder_16bit(
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [7:0] sum_low;
    wire [7:0] sum_high;
    wire c1, c2, c3;

    // Instantiate two 8-bit adders
    adder_8bit u_adder_low (
        .a(a[7:0]),
        .b(b[7:0]),
        .Cin(Cin),
        .y(sum_low),
        .Co(c1)
    );

    adder_8bit u_adder_high (
        .a(a[15:8]),
        .b(b[15:8]),
        .Cin(c1),
        .y(sum_high),
        .Co(c2)
    );

    // Combine outputs
    assign y = {sum_high, sum_low};
    assign Co = c2;
...
functional details 
[stdout]
===========Test completed with          43 / 100 failures===========
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_175047_007550_9b8266 ok ok ok failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_175047_007550_9b8266__sample_9
generated.v preview 
module adder_16bit(
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [7:0] sum_low;
    wire [7:0] sum_high;
    wire c1, c2, c3;

    // Instantiate two 8-bit adders
    adder_8bit u_adder_low (
        .a(a[7:0]),
        .b(b[7:0]),
        .Cin(Cin),
        .y(sum_low),
        .Co(c1)
    );

    adder_8bit u_adder_high (
        .a(a[15:8]),
        .b(b[15:8]),
        .Cin(c1),
        .y(sum_high),
        .Co(c2)
    );

    // Combine outputs
    assign y = {sum_high, sum_low};
    assign Co = c2;
...
functional details 
[stdout]
===========Test completed with          43 / 100 failures===========
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_175047_007550_9b8266 ok ok ok failed failed synthesis 500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_175047_007550_9b8266__sample_10
generated.v preview 
module adder_16bit(
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [7:0] sum_low;
    wire [7:0] sum_high;
    wire c1, c2, c3;

    // Instantiate two 8-bit adders
    adder_8bit u_adder_low (
        .a(a[7:0]),
        .b(b[7:0]),
        .Cin(Cin),
        .y(sum_low),
        .Co(c1)
    );

    adder_8bit u_adder_high (
        .a(a[15:8]),
        .b(b[15:8]),
        .Cin(c1),
        .y(sum_high),
        .Co(c2)
    );

    // Combine outputs
    assign y = {sum_high, sum_low};
    assign Co = c2;
...
functional details 
[stdout]
===========Test completed with          43 / 100 failures===========
synthesis details 
[error]
500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.submit_failed",
    "message": "500 Server Error: Internal Server Error for url: http://openlane-runner:8081/jobs",
    "retryable": true,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}