13_rtllm_arithmetic / task_06 | verified_adder_64bit
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_175047_007550_9b8266__sample_1
generated.v previewmodule verified_adder_64bit (
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_pipe0, addb_pipe0;
reg i_en_pipe0;
reg [63:0] adda_pipe1, addb_pipe1;
reg i_en_pipe1;
reg [63:0] adda_pipe2, addb_pipe2;
reg i_en_pipe2;
reg [63:0] adda_pipe3, addb_pipe3;
reg i_en_pipe3;
reg [63:0] adda_pipe4, addb_pipe4;
reg i_en_pipe4;
reg [63:0] adda_pipe5, addb_pipe5;
reg i_en_pipe5;
reg [63:0] adda_pipe6, addb_pipe6;
reg i_en_pipe6;
reg [63:0] adda_pipe7, addb_pipe7;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_175047_007550_9b8266__sample_2
generated.v previewmodule verified_adder_64bit (
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_pipe0, addb_pipe0;
reg i_en_pipe0;
reg [63:0] adda_pipe1, addb_pipe1;
reg i_en_pipe1;
reg [63:0] adda_pipe2, addb_pipe2;
reg i_en_pipe2;
reg [63:0] adda_pipe3, addb_pipe3;
reg i_en_pipe3;
reg [63:0] adda_pipe4, addb_pipe4;
reg i_en_pipe4;
reg [63:0] adda_pipe5, addb_pipe5;
reg i_en_pipe5;
reg [63:0] adda_pipe6, addb_pipe6;
reg i_en_pipe6;
reg [63:0] adda_pipe7, addb_pipe7;
reg i_en_pipe7;
reg [64:0] sum_pipe0, sum_pipe1, sum_pipe2, sum_pipe3, sum_pipe4, sum_pipe5, sum_pipe6, sum_pipe7;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
i_en_pipe0 <= 1'b0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_175047_007550_9b8266__sample_3
generated.v previewmodule verified_adder_64bit (
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_pipe0, addb_pipe0;
reg [63:0] adda_pipe1, addb_pipe1;
reg [63:0] adda_pipe2, addb_pipe2;
reg [63:0] adda_pipe3, addb_pipe3;
reg [63:0] adda_pipe4, addb_pipe4;
reg [63:0] adda_pipe5, addb_pipe5;
reg [63:0] adda_pipe6, addb_pipe6;
reg [63:0] adda_pipe7, addb_pipe7;
reg i_en_pipe0, i_en_pipe1, i_en_pipe2, i_en_pipe3;
reg i_en_pipe4, i_en_pipe5, i_en_pipe6, i_en_pipe7;
reg [64:0] sum_pipe0, sum_pipe1, sum_pipe2, sum_pipe3;
reg [64:0] sum_pipe4, sum_pipe5, sum_pipe6, sum_pipe7;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
adda_pipe0 <= 0;
addb_pipe0 <= 0;
i_en_pipe0 <= 0;
i_en_pipe1 <= 0;
i_en_pipe2 <= 0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_175047_007550_9b8266__sample_4
generated.v previewmodule verified_adder_64bit (
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_pipe0, addb_pipe0;
reg [63:0] adda_pipe1, addb_pipe1;
reg [63:0] adda_pipe2, addb_pipe2;
reg [63:0] adda_pipe3, addb_pipe3;
reg [63:0] adda_pipe4, addb_pipe4;
reg [63:0] adda_pipe5, addb_pipe5;
reg [63:0] adda_pipe6, addb_pipe6;
reg [63:0] adda_pipe7, addb_pipe7;
reg i_en_pipe0, i_en_pipe1, i_en_pipe2, i_en_pipe3;
reg i_en_pipe4, i_en_pipe5, i_en_pipe6, i_en_pipe7;
reg [64:0] sum_pipe0, sum_pipe1, sum_pipe2, sum_pipe3;
reg [64:0] sum_pipe4, sum_pipe5, sum_pipe6, sum_pipe7;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
adda_pipe0 <= 0;
addb_pipe0 <= 0;
i_en_pipe0 <= 0;
i_en_pipe1 <= 0;
i_en_pipe2 <= 0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260426_175047_007550_9b8266 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:136: error: part select carry2[1:63] is out of order. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_175047_007550_9b8266__sample_5
generated.v previewmodule verified_adder_64bit (
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_pipe0, addb_pipe0;
reg i_en_pipe0;
reg [63:0] adda_pipe1, addb_pipe1;
reg i_en_pipe1;
reg [63:0] adda_pipe2, addb_pipe2;
reg i_en_pipe2;
reg [63:0] adda_pipe3, addb_pipe3;
reg i_en_pipe3;
reg [63:0] adda_pipe4, addb_pipe4;
reg i_en_pipe4;
reg [63:0] adda_pipe5, addb_pipe5;
reg i_en_pipe5;
reg [63:0] adda_pipe6, addb_pipe6;
reg i_en_pipe6;
reg [63:0] adda_pipe7, addb_pipe7;
...
syntax details[stderr] /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:136: error: part select carry2[1:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:137: error: part select result_pipe3[1:63] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:137: error: part select carry3[1:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:138: error: part select result_pipe4[1:63] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:138: error: part select carry4[1:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:139: error: part select result_pipe5[1:63] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:139: error: part select carry5[1:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:140: error: part select result_pipe6[1:63] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:140: error: part select carry6[1:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:141: error: part select result_pipe7[1:63] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:141: error: part select carry7[1:63] is out of order. 40 error(s) during elaboration. functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:136: error: part select carry2[1:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:137: error: part select result_pipe3[1:63] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:137: error: part select carry3[1:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:138: error: part select result_pipe4[1:63] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:138: error: part select carry4[1:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:139: error: part select result_pipe5[1:63] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:139: error: part select carry5[1:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:140: error: part select result_pipe6[1:63] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:140: error: part select carry6[1:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:141: error: part select result_pipe7[1:63] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:141: error: part select carry7[1:63] is out of order.\n40 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_175047_007550_9b8266__sample_6
generated.v previewmodule verified_adder_64bit (
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_pipe0, addb_pipe0;
reg [63:0] adda_pipe1, addb_pipe1;
reg [63:0] adda_pipe2, addb_pipe2;
reg [63:0] adda_pipe3, addb_pipe3;
reg [63:0] adda_pipe4, addb_pipe4;
reg [63:0] adda_pipe5, addb_pipe5;
reg [63:0] adda_pipe6, addb_pipe6;
reg [63:0] adda_pipe7, addb_pipe7;
reg i_en_pipe0, i_en_pipe1, i_en_pipe2, i_en_pipe3;
reg i_en_pipe4, i_en_pipe5, i_en_pipe6, i_en_pipe7;
reg [64:0] sum_pipe0, sum_pipe1, sum_pipe2, sum_pipe3;
reg [64:0] sum_pipe4, sum_pipe5, sum_pipe6, sum_pipe7;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
adda_pipe0 <= 0;
addb_pipe0 <= 0;
i_en_pipe0 <= 0;
o_en <= 0;
result <= 0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260426_175047_007550_9b8266 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:136: error: part select carry2[0:63] is out of order. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_175047_007550_9b8266__sample_7
generated.v previewmodule verified_adder_64bit (
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_pipe0, addb_pipe0;
reg i_en_pipe0;
reg [63:0] adda_pipe1, addb_pipe1;
reg i_en_pipe1;
reg [63:0] adda_pipe2, addb_pipe2;
reg i_en_pipe2;
reg [63:0] adda_pipe3, addb_pipe3;
reg i_en_pipe3;
reg [63:0] adda_pipe4, addb_pipe4;
reg i_en_pipe4;
reg [63:0] adda_pipe5, addb_pipe5;
reg i_en_pipe5;
reg [63:0] adda_pipe6, addb_pipe6;
reg i_en_pipe6;
reg [63:0] adda_pipe7, addb_pipe7;
...
syntax details[stderr] /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:136: error: part select carry2[0:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:137: error: part select result_pipe3[1:64] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:137: error: part select carry3[0:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:138: error: part select result_pipe4[1:64] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:138: error: part select carry4[0:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:139: error: part select result_pipe5[1:64] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:139: error: part select carry5[0:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:140: error: part select result_pipe6[1:64] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:140: error: part select carry6[0:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:141: error: part select result_pipe7[1:64] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:141: error: part select carry7[0:63] is out of order. 40 error(s) during elaboration. functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:136: error: part select carry2[0:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:137: error: part select result_pipe3[1:64] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:137: error: part select carry3[0:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:138: error: part select result_pipe4[1:64] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:138: error: part select carry4[0:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:139: error: part select result_pipe5[1:64] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:139: error: part select carry5[0:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:140: error: part select result_pipe6[1:64] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:140: error: part select carry6[0:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:141: error: part select result_pipe7[1:64] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:141: error: part select carry7[0:63] is out of order.\n40 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_175047_007550_9b8266__sample_8
generated.v previewmodule verified_adder_64bit (
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_pipe0, addb_pipe0;
reg i_en_pipe0;
reg [63:0] adda_pipe1, addb_pipe1;
reg i_en_pipe1;
reg [63:0] adda_pipe2, addb_pipe2;
reg i_en_pipe2;
reg [63:0] adda_pipe3, addb_pipe3;
reg i_en_pipe3;
reg [63:0] adda_pipe4, addb_pipe4;
reg i_en_pipe4;
reg [63:0] adda_pipe5, addb_pipe5;
reg i_en_pipe5;
reg [63:0] adda_pipe6, addb_pipe6;
reg i_en_pipe6;
reg [63:0] adda_pipe7, addb_pipe7;
reg i_en_pipe7;
reg [64:0] sum_pipe0, sum_pipe1, sum_pipe2, sum_pipe3, sum_pipe4, sum_pipe5, sum_pipe6, sum_pipe7;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
i_en_pipe0 <= 1'b0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260426_175047_007550_9b8266 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:136: error: part select carry2[0:63] is out of order. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_175047_007550_9b8266__sample_9
generated.v previewmodule verified_adder_64bit (
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_pipe0, addb_pipe0;
reg i_en_pipe0;
reg [63:0] adda_pipe1, addb_pipe1;
reg i_en_pipe1;
reg [63:0] adda_pipe2, addb_pipe2;
reg i_en_pipe2;
reg [63:0] adda_pipe3, addb_pipe3;
reg i_en_pipe3;
reg [63:0] adda_pipe4, addb_pipe4;
reg i_en_pipe4;
reg [63:0] adda_pipe5, addb_pipe5;
reg i_en_pipe5;
reg [63:0] adda_pipe6, addb_pipe6;
reg i_en_pipe6;
reg [63:0] adda_pipe7, addb_pipe7;
...
syntax details[stderr] /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:136: error: part select carry2[0:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:137: error: part select result_pipe3[1:64] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:137: error: part select carry3[0:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:138: error: part select result_pipe4[1:64] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:138: error: part select carry4[0:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:139: error: part select result_pipe5[1:64] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:139: error: part select carry5[0:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:140: error: part select result_pipe6[1:64] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:140: error: part select carry6[0:63] is out of order. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:141: error: part select result_pipe7[1:64] is reversed. /data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:141: error: part select carry7[0:63] is out of order. 40 error(s) during elaboration. functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:136: error: part select carry2[0:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:137: error: part select result_pipe3[1:64] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:137: error: part select carry3[0:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:138: error: part select result_pipe4[1:64] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:138: error: part select carry4[0:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:139: error: part select result_pipe5[1:64] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:139: error: part select carry5[0:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:140: error: part select result_pipe6[1:64] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:140: error: part select carry6[0:63] is out of order.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:141: error: part select result_pipe7[1:64] is reversed.\n/data/eval/out/run_20260426_175047_007550_9b8266/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:141: error: part select carry7[0:63] is out of order.\n40 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_175047_007550_9b8266__sample_10
generated.v previewmodule verified_adder_64bit (
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_pipe0, addb_pipe0;
reg [63:0] adda_pipe1, addb_pipe1;
reg [63:0] adda_pipe2, addb_pipe2;
reg [63:0] adda_pipe3, addb_pipe3;
reg [63:0] adda_pipe4, addb_pipe4;
reg [63:0] adda_pipe5, addb_pipe5;
reg [63:0] adda_pipe6, addb_pipe6;
reg [63:0] adda_pipe7, addb_pipe7;
reg i_en_pipe0, i_en_pipe1, i_en_pipe2, i_en_pipe3;
reg i_en_pipe4, i_en_pipe5, i_en_pipe6, i_en_pipe7;
reg [64:0] sum_pipe0, sum_pipe1, sum_pipe2, sum_pipe3;
reg [64:0] sum_pipe4, sum_pipe5, sum_pipe6, sum_pipe7;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
adda_pipe0 <= 0;
addb_pipe0 <= 0;
i_en_pipe0 <= 0;
o_en <= 0;
result <= 0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|