13_rtllm_arithmetic / task_10 | verified_radix2_div
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_175047_007550_9b8266__sample_1
generated.v previewmodule verified_radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [15:0] SR;
reg [7:0] cnt;
reg start_cnt;
reg [7:0] NEG_DIVISOR;
reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] temp_SR;
reg carry_out;
always @(posedge clk or posedge rst) begin
if (rst) begin
SR <= 16'b0;
cnt <= 8'b0;
start_cnt <= 1'b0;
res_valid <= 1'b0;
result <= 16'b0;
end else begin
if (opn_valid && !res_valid) begin
// Save inputs
abs_dividend <= dividend;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div
3 error(s) during elaboration.
*** These modules were missing:
radix2_div referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div\n3 error(s) during elaboration.\n*** These modules were missing:\n radix2_div referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_175047_007550_9b8266__sample_2
generated.v previewmodule verified_radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [15:0] SR;
reg [7:0] cnt;
reg start_cnt;
reg [7:0] NEG_DIVISOR;
reg [7:0] ABS_DIVIDEND;
reg [7:0] ABS_DIVISOR;
reg [7:0] temp_sub;
reg carry_out;
always @(posedge clk or posedge rst) begin
if (rst) begin
SR <= 16'b0;
cnt <= 8'b0;
start_cnt <= 1'b0;
res_valid <= 1'b0;
result <= 16'b0;
end else begin
if (opn_valid && !res_valid) begin
// Save inputs
ABS_DIVIDEND <= dividend;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div
3 error(s) during elaboration.
*** These modules were missing:
radix2_div referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div\n3 error(s) during elaboration.\n*** These modules were missing:\n radix2_div referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_175047_007550_9b8266__sample_3
generated.v previewmodule verified_radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [15:0] SR;
reg [7:0] cnt;
reg start_cnt;
reg [7:0] NEG_DIVISOR;
reg [7:0] ABS_DIVIDEND;
reg [7:0] ABS_DIVISOR;
reg [7:0] temp_sub;
reg carry_out;
always @(posedge clk or posedge rst) begin
if (rst) begin
SR <= 16'b0;
cnt <= 8'b0;
start_cnt <= 1'b0;
res_valid <= 1'b0;
result <= 16'b0;
end else begin
if (opn_valid && !res_valid) begin
// Save inputs
ABS_DIVIDEND <= dividend;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div
3 error(s) during elaboration.
*** These modules were missing:
radix2_div referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div\n3 error(s) during elaboration.\n*** These modules were missing:\n radix2_div referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_175047_007550_9b8266__sample_4
generated.v previewmodule verified_radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [15:0] SR;
reg [7:0] cnt;
reg start_cnt;
reg [7:0] NEG_DIVISOR;
reg [7:0] ABS_DIVIDEND;
reg [7:0] ABS_DIVISOR;
reg [7:0] temp_sub;
reg carry_out;
always @(posedge clk or posedge rst) begin
if (rst) begin
SR <= 16'b0;
cnt <= 8'b0;
start_cnt <= 1'b0;
res_valid <= 1'b0;
result <= 16'b0;
end else begin
if (opn_valid && !res_valid) begin
// Save inputs
ABS_DIVIDEND <= dividend;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div
3 error(s) during elaboration.
*** These modules were missing:
radix2_div referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div\n3 error(s) during elaboration.\n*** These modules were missing:\n radix2_div referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_175047_007550_9b8266__sample_5
generated.v previewmodule verified_radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [15:0] SR;
reg [7:0] cnt;
reg start_cnt;
reg [7:0] NEG_DIVISOR;
reg [7:0] ABS_DIVIDEND;
reg [7:0] ABS_DIVISOR;
reg [7:0] temp_sub;
reg carry_out;
always @(posedge clk or posedge rst) begin
if (rst) begin
SR <= 16'b0;
cnt <= 8'b0;
start_cnt <= 1'b0;
res_valid <= 1'b0;
result <= 16'b0;
end else begin
if (opn_valid && !res_valid) begin
// Save inputs
ABS_DIVIDEND <= dividend;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div
3 error(s) during elaboration.
*** These modules were missing:
radix2_div referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div\n3 error(s) during elaboration.\n*** These modules were missing:\n radix2_div referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_175047_007550_9b8266__sample_6
generated.v previewmodule verified_radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [15:0] SR;
reg [7:0] cnt;
reg start_cnt;
reg [7:0] NEG_DIVISOR;
reg [7:0] ABS_DIVIDEND;
reg [7:0] ABS_DIVISOR;
reg [7:0] temp_sub;
reg carry_out;
always @(posedge clk or posedge rst) begin
if (rst) begin
SR <= 16'b0;
cnt <= 8'b0;
start_cnt <= 1'b0;
res_valid <= 1'b0;
result <= 16'b0;
end else begin
if (opn_valid && !res_valid) begin
// Save inputs
ABS_DIVIDEND <= dividend;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div
3 error(s) during elaboration.
*** These modules were missing:
radix2_div referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div\n3 error(s) during elaboration.\n*** These modules were missing:\n radix2_div referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_175047_007550_9b8266__sample_7
generated.v previewmodule verified_radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [15:0] SR;
reg [7:0] cnt;
reg start_cnt;
reg [7:0] NEG_DIVISOR;
reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] temp_SR;
reg carry_out;
always @(posedge clk or posedge rst) begin
if (rst) begin
SR <= 16'b0;
cnt <= 8'b0;
start_cnt <= 1'b0;
res_valid <= 1'b0;
result <= 16'b0;
end else begin
if (opn_valid && !res_valid) begin
// Save inputs
abs_dividend <= dividend;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div
3 error(s) during elaboration.
*** These modules were missing:
radix2_div referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div\n3 error(s) during elaboration.\n*** These modules were missing:\n radix2_div referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_175047_007550_9b8266__sample_8
generated.v previewmodule verified_radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [15:0] SR;
reg [7:0] cnt;
reg start_cnt;
reg [7:0] NEG_DIVISOR;
reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [7:0] dividend_reg;
reg [7:0] divisor_reg;
reg [15:0] temp_result;
always @(posedge clk or posedge rst) begin
if (rst) begin
SR <= 16'b0;
cnt <= 8'b0;
start_cnt <= 1'b0;
res_valid <= 1'b0;
result <= 16'b0;
end else begin
if (opn_valid && !res_valid) begin
dividend_reg <= dividend;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div
3 error(s) during elaboration.
*** These modules were missing:
radix2_div referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div\n3 error(s) during elaboration.\n*** These modules were missing:\n radix2_div referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_175047_007550_9b8266__sample_9
generated.v previewmodule verified_radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [15:0] SR;
reg [7:0] cnt;
reg start_cnt;
reg [7:0] NEG_DIVISOR;
reg [7:0] ABS_DIVIDEND;
reg [7:0] ABS_DIVISOR;
reg [7:0] temp_sub;
reg carry_out;
always @(posedge clk or posedge rst) begin
if (rst) begin
SR <= 16'b0;
cnt <= 8'b0;
start_cnt <= 1'b0;
res_valid <= 1'b0;
result <= 16'b0;
end else begin
if (opn_valid && !res_valid) begin
// Save inputs
ABS_DIVIDEND <= dividend;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div
3 error(s) during elaboration.
*** These modules were missing:
radix2_div referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div\n3 error(s) during elaboration.\n*** These modules were missing:\n radix2_div referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_175047_007550_9b8266__sample_10
generated.v previewmodule verified_radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [15:0] SR;
reg [7:0] cnt;
reg start_cnt;
reg [7:0] NEG_DIVISOR;
reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [7:0] dividend_reg;
reg [7:0] divisor_reg;
reg [15:0] temp_result;
always @(posedge clk or posedge rst) begin
if (rst) begin
SR <= 16'b0;
cnt <= 8'b0;
start_cnt <= 1'b0;
res_valid <= 1'b0;
result <= 16'b0;
abs_dividend <= 8'b0;
abs_divisor <= 8'b0;
dividend_reg <= 8'b0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div
3 error(s) during elaboration.
*** These modules were missing:
radix2_div referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div\n3 error(s) during elaboration.\n*** These modules were missing:\n radix2_div referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|