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qwen3-coder:30b | RAG off

13_rtllm_arithmetic / task_11 | verified_multi_16bit

benchmarkrtllm
task_idrtllm/13_rtllm_arithmetic/task_11
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260426_175047_007550_9b8266

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_175047_007550_9b8266 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_11\samples\run_20260426_175047_007550_9b8266__sample_1
generated.v preview 
module verified_multi_16bit (
    input clk,
    input rst_n,
    input start,
    input [15:0] ain,
    input [15:0] bin,
    output reg [31:0] yout,
    output reg done
);

reg [15:0] areg;
reg [15:0] breg;
reg [31:0] yout_r;
reg [4:0] i;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        i <= 0;
        done <= 0;
        areg <= 0;
        breg <= 0;
        yout_r <= 0;
    end else begin
        if (start) begin
            if (i < 17) begin
                i <= i + 1;
            end
            if (i == 0) begin
                areg <= ain;
                breg <= bin;
            end else if (i > 0 && i < 17) begin
                if (areg[i-1])
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
3 error(s) during elaboration.
*** These modules were missing:
        multi_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        multi_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_175047_007550_9b8266 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_11\samples\run_20260426_175047_007550_9b8266__sample_2
generated.v preview 
module verified_multi_16bit (
    input        clk,
    input        rst_n,
    input        start,
    input  [15:0] ain,
    input  [15:0] bin,
    output [31:0] yout,
    output        done
);

reg  [15:0] areg;
reg  [15:0] breg;
reg  [31:0] yout_r;
reg  [4:0]  i;
reg         done_r;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        areg    <= 16'b0;
        breg    <= 16'b0;
        yout_r  <= 32'b0;
        i       <= 5'b0;
        done_r  <= 1'b0;
    end else begin
        if (start) begin
            if (i < 17) begin
                i <= i + 1;
            end
            if (i == 0) begin
                areg <= ain;
                breg <= bin;
            end else if (i > 0 && i < 17) begin
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
3 error(s) during elaboration.
*** These modules were missing:
        multi_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        multi_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_175047_007550_9b8266 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_11\samples\run_20260426_175047_007550_9b8266__sample_3
generated.v preview 
module verified_multi_16bit (
    input clk,
    input rst_n,
    input start,
    input [15:0] ain,
    input [15:0] bin,
    output [31:0] yout,
    output done
);

reg [15:0] areg;
reg [15:0] breg;
reg [31:0] yout_r;
reg [4:0] i;
reg done_r;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        areg <= 16'b0;
        breg <= 16'b0;
        yout_r <= 32'b0;
        i <= 5'b0;
        done_r <= 1'b0;
    end else begin
        if (start) begin
            if (i < 17) begin
                i <= i + 1;
            end
            if (i == 0) begin
                areg <= ain;
                breg <= bin;
            end else if (i > 0 && i < 17) begin
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
3 error(s) during elaboration.
*** These modules were missing:
        multi_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        multi_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_175047_007550_9b8266 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_11\samples\run_20260426_175047_007550_9b8266__sample_4
generated.v preview 
module verified_multi_16bit (
    input        clk,
    input        rst_n,
    input        start,
    input  [15:0] ain,
    input  [15:0] bin,
    output [31:0] yout,
    output        done
);

reg  [15:0] areg;
reg  [15:0] breg;
reg  [31:0] yout_r;
reg  [4:0]  i;
reg         done_r;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        areg    <= 16'b0;
        breg    <= 16'b0;
        yout_r  <= 32'b0;
        i       <= 5'b0;
        done_r  <= 1'b0;
    end else begin
        if (start) begin
            if (i < 17) begin
                i <= i + 1;
            end
            if (i == 0) begin
                areg <= ain;
                breg <= bin;
            end else if (i > 0 && i < 17) begin
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
3 error(s) during elaboration.
*** These modules were missing:
        multi_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        multi_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_175047_007550_9b8266 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_11\samples\run_20260426_175047_007550_9b8266__sample_5
generated.v preview 
module verified_multi_16bit (
    input        clk,
    input        rst_n,
    input        start,
    input  [15:0] ain,
    input  [15:0] bin,
    output [31:0] yout,
    output        done
);

reg  [15:0] areg;
reg  [15:0] breg;
reg  [31:0] yout_r;
reg  [4:0]  i;
reg         done_r;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        areg    <= 16'b0;
        breg    <= 16'b0;
        yout_r  <= 32'b0;
        i       <= 5'b0;
        done_r  <= 1'b0;
    end else begin
        if (start) begin
            if (i < 17) begin
                i <= i + 1;
            end
            if (i == 0) begin
                areg <= ain;
                breg <= bin;
            end else if (i > 0 && i < 17) begin
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
3 error(s) during elaboration.
*** These modules were missing:
        multi_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        multi_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_175047_007550_9b8266 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_11\samples\run_20260426_175047_007550_9b8266__sample_6
generated.v preview 
module verified_multi_16bit (
    input        clk,
    input        rst_n,
    input        start,
    input  [15:0] ain,
    input  [15:0] bin,
    output [31:0] yout,
    output        done
);

reg  [15:0] areg;
reg  [15:0] breg;
reg  [31:0] yout_r;
reg  [4:0]  i;
reg         done_r;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        areg    <= 16'b0;
        breg    <= 16'b0;
        yout_r  <= 32'b0;
        i       <= 5'b0;
        done_r  <= 1'b0;
    end else begin
        if (start) begin
            if (i < 17) begin
                i <= i + 1;
            end
            if (i == 0) begin
                areg <= ain;
                breg <= bin;
            end else if (i > 0 && i < 17) begin
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
3 error(s) during elaboration.
*** These modules were missing:
        multi_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        multi_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_175047_007550_9b8266 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_11\samples\run_20260426_175047_007550_9b8266__sample_7
generated.v preview 
module verified_multi_16bit (
    input        clk,
    input        rst_n,
    input        start,
    input  [15:0] ain,
    input  [15:0] bin,
    output [31:0] yout,
    output        done
);

reg  [15:0] areg;
reg  [15:0] breg;
reg  [31:0] yout_r;
reg  [4:0]  i;
reg         done_r;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        areg    <= 16'b0;
        breg    <= 16'b0;
        yout_r  <= 32'b0;
        i       <= 5'b0;
        done_r  <= 1'b0;
    end else begin
        if (start) begin
            if (i < 17) begin
                i <= i + 1;
            end
            if (i == 0) begin
                areg <= ain;
                breg <= bin;
            end else if (i > 0 && i < 17) begin
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
3 error(s) during elaboration.
*** These modules were missing:
        multi_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        multi_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_175047_007550_9b8266 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_11\samples\run_20260426_175047_007550_9b8266__sample_8
generated.v preview 
module verified_multi_16bit (
    input        clk,
    input        rst_n,
    input        start,
    input  [15:0] ain,
    input  [15:0] bin,
    output [31:0] yout,
    output        done
);

reg  [15:0] areg;
reg  [15:0] breg;
reg  [31:0] yout_r;
reg  [4:0]  i;
reg         done_r;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        areg    <= 16'b0;
        breg    <= 16'b0;
        yout_r  <= 32'b0;
        i       <= 5'b0;
        done_r  <= 1'b0;
    end else begin
        if (start) begin
            if (i < 17) begin
                i <= i + 1;
            end
            if (i == 0) begin
                areg <= ain;
                breg <= bin;
            end else if (i > 0 && i < 17) begin
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
3 error(s) during elaboration.
*** These modules were missing:
        multi_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        multi_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_175047_007550_9b8266 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_11\samples\run_20260426_175047_007550_9b8266__sample_9
generated.v preview 
module verified_multi_16bit (
    input        clk,
    input        rst_n,
    input        start,
    input  [15:0] ain,
    input  [15:0] bin,
    output [31:0] yout,
    output        done
);

reg  [15:0] areg;
reg  [15:0] breg;
reg  [31:0] yout_r;
reg  [4:0]  i;
reg         done_r;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        areg    <= 16'b0;
        breg    <= 16'b0;
        yout_r  <= 32'b0;
        i       <= 5'b0;
        done_r  <= 1'b0;
    end else begin
        if (start) begin
            if (i < 17) begin
                i <= i + 1;
            end
            if (i == 0) begin
                areg <= ain;
                breg <= bin;
            end else if (i > 0 && i < 17) begin
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
3 error(s) during elaboration.
*** These modules were missing:
        multi_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        multi_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_175047_007550_9b8266 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_11\samples\run_20260426_175047_007550_9b8266__sample_10
generated.v preview 
module verified_multi_16bit (
    input        clk,
    input        rst_n,
    input        start,
    input  [15:0] ain,
    input  [15:0] bin,
    output [31:0] yout,
    output        done
);

reg  [15:0] areg;
reg  [15:0] breg;
reg  [31:0] yout_r;
reg  [4:0]  i;
reg         done_r;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        areg    <= 16'b0;
        breg    <= 16'b0;
        yout_r  <= 32'b0;
        i       <= 5'b0;
        done_r  <= 1'b0;
    end else begin
        if (start) begin
            if (i < 17) begin
                i <= i + 1;
            end
            if (i == 0) begin
                areg <= ain;
                breg <= bin;
            end else if (i > 0 && i < 17) begin
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit
3 error(s) during elaboration.
*** These modules were missing:
        multi_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_11/tb.v:17: error: Unknown module type: multi_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        multi_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}