13_rtllm_memory / task_01 | verified_asyn_fifo
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_memory__task_01\samples\run_20260426_175047_007550_9b8266__sample_1
generated.v previewmodule verified_asyn_fifo (
input wclk,
input rclk,
input wrstn,
input rrstn,
input winc,
input rinc,
input [7:0] wdata,
output reg [7:0] rdata,
output reg wfull,
output reg rempty
);
parameter WIDTH = 8;
parameter DEPTH = 16;
reg [3:0] wptr;
reg [3:0] rptr;
reg [3:0] wptr_buff;
reg [3:0] rptr_buff;
reg [3:0] wptr_syn;
reg [3:0] rptr_syn;
reg [3:0] waddr_bin;
reg [3:0] raddr_bin;
wire [3:0] waddr_gray;
wire [3:0] raddr_gray;
reg wen;
reg ren;
...
functional details[stderr] /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_memory__task_01\samples\run_20260426_175047_007550_9b8266__sample_2
generated.v previewmodule verified_asyn_fifo (
input wclk,
input rclk,
input wrstn,
input rrstn,
input winc,
input rinc,
input [7:0] wdata,
output reg [7:0] rdata,
output reg wfull,
output reg rempty
);
parameter WIDTH = 8;
parameter DEPTH = 16;
reg [3:0] wptr;
reg [3:0] rptr;
reg [3:0] wptr_buff;
reg [3:0] rptr_buff;
reg [3:0] wptr_syn;
reg [3:0] rptr_syn;
reg [3:0] waddr_bin;
reg [3:0] raddr_bin;
wire [3:0] waddr_gray;
wire [3:0] raddr_gray;
reg [7:0] RAM_MEM [0:15];
wire wen;
...
functional details[stderr] /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_memory__task_01\samples\run_20260426_175047_007550_9b8266__sample_3
generated.v previewmodule verified_asyn_fifo (
input wclk,
input rclk,
input wrstn,
input rrstn,
input winc,
input rinc,
input [7:0] wdata,
output reg [7:0] rdata,
output reg wfull,
output reg rempty
);
parameter WIDTH = 8;
parameter DEPTH = 16;
reg [3:0] wptr;
reg [3:0] rptr;
reg [3:0] wptr_buff;
reg [3:0] rptr_buff;
reg [3:0] wptr_syn;
reg [3:0] rptr_syn;
reg [3:0] waddr_bin;
reg [3:0] raddr_bin;
wire [3:0] waddr_gray;
wire [3:0] raddr_gray;
reg [7:0] RAM_MEM [0:15];
wire wen;
...
functional details[stderr] /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_memory__task_01\samples\run_20260426_175047_007550_9b8266__sample_4
generated.v previewmodule verified_asyn_fifo (
input wclk,
input rclk,
input wrstn,
input rrstn,
input winc,
input rinc,
input [7:0] wdata,
output reg [7:0] rdata,
output reg wfull,
output reg rempty
);
parameter WIDTH = 8;
parameter DEPTH = 16;
reg [3:0] wptr;
reg [3:0] rptr;
reg [3:0] wptr_buff;
reg [3:0] rptr_buff;
reg [3:0] wptr_syn;
reg [3:0] rptr_syn;
reg [3:0] waddr_bin;
reg [3:0] raddr_bin;
wire [3:0] waddr_gray;
wire [3:0] raddr_gray;
reg [7:0] RAM_MEM [0:15];
wire wen;
...
functional details[stderr] /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_memory__task_01\samples\run_20260426_175047_007550_9b8266__sample_5
generated.v previewmodule verified_asyn_fifo (
input wclk,
input rclk,
input wrstn,
input rrstn,
input winc,
input rinc,
input [7:0] wdata,
output reg [7:0] rdata,
output reg wfull,
output reg rempty
);
parameter WIDTH = 8;
parameter DEPTH = 16;
reg [3:0] wptr;
reg [3:0] rptr;
reg [3:0] wptr_buff;
reg [3:0] rptr_buff;
reg [3:0] wptr_syn;
reg [3:0] rptr_syn;
reg [3:0] waddr_bin;
reg [3:0] raddr_bin;
wire [3:0] waddr_bin_next;
wire [3:0] raddr_bin_next;
reg [7:0] RAM_MEM [0:15];
wire wen;
...
functional details[stderr] /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_memory__task_01\samples\run_20260426_175047_007550_9b8266__sample_6
generated.v previewmodule verified_asyn_fifo (
input wclk,
input rclk,
input wrstn,
input rrstn,
input winc,
input rinc,
input [7:0] wdata,
output reg [7:0] rdata,
output reg wfull,
output reg rempty
);
parameter WIDTH = 8;
parameter DEPTH = 16;
reg [3:0] wptr;
reg [3:0] rptr;
reg [3:0] wptr_buff;
reg [3:0] rptr_buff;
reg [3:0] wptr_syn;
reg [3:0] rptr_syn;
reg [3:0] waddr_bin;
reg [3:0] raddr_bin;
wire [3:0] waddr_gray;
wire [3:0] raddr_gray;
reg [7:0] RAM_MEM [0:15];
wire wen;
...
functional details[stderr] /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_memory__task_01\samples\run_20260426_175047_007550_9b8266__sample_7
generated.v previewmodule verified_asyn_fifo (
input wclk,
input rclk,
input wrstn,
input rrstn,
input winc,
input rinc,
input [7:0] wdata,
output reg [7:0] rdata,
output reg wfull,
output reg rempty
);
parameter WIDTH = 8;
parameter DEPTH = 16;
reg [3:0] wptr;
reg [3:0] rptr;
reg [3:0] wptr_buff;
reg [3:0] rptr_buff;
reg [3:0] wptr_syn;
reg [3:0] rptr_syn;
reg [3:0] waddr_bin;
reg [3:0] raddr_bin;
wire [3:0] waddr_gray;
wire [3:0] raddr_gray;
reg [7:0] RAM_MEM [0:15];
wire wen;
...
functional details[stderr] /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_memory__task_01\samples\run_20260426_175047_007550_9b8266__sample_8
generated.v previewmodule verified_asyn_fifo (
input wclk,
input rclk,
input wrstn,
input rrstn,
input winc,
input rinc,
input [7:0] wdata,
output reg [7:0] rdata,
output reg wfull,
output reg rempty
);
parameter WIDTH = 8;
parameter DEPTH = 16;
reg [3:0] wptr;
reg [3:0] rptr;
reg [3:0] wptr_buff;
reg [3:0] rptr_buff;
reg [3:0] wptr_syn;
reg [3:0] rptr_syn;
reg [3:0] waddr_bin;
reg [3:0] raddr_bin;
wire [3:0] waddr_gray;
wire [3:0] raddr_gray;
reg [7:0] RAM_MEM [0:15];
wire wen;
...
functional details[stderr] /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_memory__task_01\samples\run_20260426_175047_007550_9b8266__sample_9
generated.v previewmodule verified_asyn_fifo (
input wclk,
input rclk,
input wrstn,
input rrstn,
input winc,
input rinc,
input [7:0] wdata,
output reg [7:0] rdata,
output reg wfull,
output reg rempty
);
parameter WIDTH = 8;
parameter DEPTH = 16;
reg [3:0] wptr;
reg [3:0] rptr;
reg [3:0] wptr_buff;
reg [3:0] rptr_buff;
reg [3:0] wptr_syn;
reg [3:0] rptr_syn;
reg [3:0] waddr_bin;
reg [3:0] raddr_bin;
wire [3:0] waddr_gray;
wire [3:0] raddr_gray;
reg [7:0] RAM_MEM [0:15];
wire wen;
...
functional details[stderr] /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260426_175047_007550_9b8266 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_memory__task_01\samples\run_20260426_175047_007550_9b8266__sample_10
generated.v previewmodule verified_asyn_fifo (
input wclk,
input rclk,
input wrstn,
input rrstn,
input winc,
input rinc,
input [7:0] wdata,
output reg [7:0] rdata,
output reg wfull,
output reg rempty
);
parameter WIDTH = 8;
parameter DEPTH = 16;
reg [3:0] wptr;
reg [3:0] rptr;
reg [3:0] wptr_buff;
reg [3:0] rptr_buff;
reg [3:0] wptr_syn;
reg [3:0] rptr_syn;
reg [3:0] waddr_bin;
reg [3:0] raddr_bin;
wire [3:0] waddr_gray;
wire [3:0] raddr_gray;
reg [7:0] RAM_MEM [0:15];
wire wen;
...
functional details[stderr] /workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported. synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_memory/task_01/tb.v:102: sorry: break statements not supported.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|