Назад к моделям Назад к профилю модели

qwen3-coder:30b | RAG on

06_reset_domain_crossing / task_62 | triple_reset_sequencer

benchmarkilyasov
task_idilyasov/06_reset_domain_crossing/task_62
samples_total33
final_success_samples3
final_success_rate_samples9.1%
functional_pass_rate_samples9.1%
synth_pass_rate_samples9.1%
source_runsrun_20260424_144121_405769_1acdc5, run_20260424_172135_562392_bd9fc2, run_20260424_230145_632624_082334, run_20260426_141859_833435_7c9834

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260424_144121_405769_1acdc5 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_144121_405769_1acdc5__sample_1
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg cpu_ready_sync1;
    reg cpu_ready_sync2;
    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
...
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_1 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_172135_562392_bd9fc2__sample_1
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg cpu_ready_sync1;
    reg cpu_ready_sync2;
    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_1 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_230145_632624_082334__sample_1
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    wire cpu_reset_ready;
    wire bus_reset_ready;
    
    // CPU domain reset logic
    reg cpu_rst_sync;
    reg cpu_rst_sync2;
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            cpu_rst_sync <= 1'b1;
            cpu_rst_sync2 <= 1'b1;
        end else begin
            cpu_rst_sync <= 1'b0;
            cpu_rst_sync2 <= cpu_rst_sync;
        end
    end
    
    // Bus domain reset logic
    reg bus_rst_sync;
    reg bus_rst_sync2;
    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_1 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_141859_833435_7c9834__sample_1
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    wire cpu_reset_ready;
    wire bus_reset_ready;
    
    // CPU domain reset logic
    reg cpu_rst_reg = 1'b1;
    reg cpu_sync_reg0 = 1'b1;
    reg cpu_sync_reg1 = 1'b1;
    
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            cpu_rst_reg <= 1'b1;
        end else begin
            cpu_rst_reg <= 1'b0;
        end
    end
    
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            cpu_sync_reg0 <= 1'b1;
            cpu_sync_reg1 <= 1'b1;
        end else begin
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260424_144121_405769_1acdc5 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_144121_405769_1acdc5__sample_2
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;
    
    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end
    
    // 2-flop synchronizer for CPU reset
    reg cpu_ready_sync1, cpu_ready_sync2;
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
            cpu_ready_sync1 <= rst_cpu_sync;
...
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_2 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_172135_562392_bd9fc2__sample_2
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;
    
    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end
    
    // 2-flop synchronizer for CPU reset
    reg cpu_ready_sync1, cpu_ready_sync2;
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
            cpu_ready_sync1 <= rst_cpu_sync;
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260424_230145_632624_082334 ok failed failed skipped failed syntax /data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:41: error: 'rst_bus_ready_sync' has already been declared in this scope.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_230145_632624_082334__sample_2
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n)
            rst_cpu_sync <= 1'b1;
        else
            rst_cpu_sync <= 1'b0;
    end

    // Bus domain reset logic
    reg rst_cpu_ready_sync;
    reg rst_bus_ready_sync;

    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_ready_sync <= 1'b1;
            rst_bus_sync <= 1'b1;
        end else begin
...
syntax details 
[stderr]
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:41: error: 'rst_bus_ready_sync' has already been declared in this scope.
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:26:      : It was declared here as a variable.
functional details 
[stderr]
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:41: error: 'rst_bus_ready_sync' has already been declared in this scope.
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:26:      : It was declared here as a variable.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:41: error: 'rst_bus_ready_sync' has already been declared in this scope.\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:26:      : It was declared here as a variable.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:41: error: 'rst_bus_ready_sync' has already been declared in this scope.\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:26:      : It was declared here as a variable.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_141859_833435_7c9834__sample_2
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n)
            rst_cpu_sync <= 1'b1;
        else
            rst_cpu_sync <= 1'b0;
    end

    // Bus domain reset logic
    reg rst_cpu_ready_sync;
    reg rst_bus_ready_sync;

    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n)
            rst_cpu_ready_sync <= 1'b1;
        else
            rst_cpu_ready_sync <= rst_cpu_sync;
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260424_144121_405769_1acdc5 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_144121_405769_1acdc5__sample_3
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;
    
    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end
    
    // 2-flop synchronizer for CPU reset
    reg cpu_ready_sync1, cpu_ready_sync2;
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
            cpu_ready_sync1 <= rst_cpu_sync;
...
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_3 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_172135_562392_bd9fc2__sample_3
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;
    
    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end
    
    // 2-flop synchronizer for CPU reset
    reg cpu_ready_sync1, cpu_ready_sync2;
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
            cpu_ready_sync1 <= rst_cpu_sync;
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_230145_632624_082334__sample_3
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;
    
    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end
    
    // 2-flop synchronizer for CPU reset
    reg cpu_ready_sync1, cpu_ready_sync2;
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
            cpu_ready_sync1 <= rst_cpu_sync;
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_141859_833435_7c9834__sample_3
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;
    
    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end
    
    // 2-flop synchronizer for CPU reset
    reg cpu_ready_sync1, cpu_ready_sync2;
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
            cpu_ready_sync1 <= rst_cpu_sync;
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_172135_562392_bd9fc2__sample_4
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;
    
    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end
    
    // 2-flop synchronizer for CPU reset
    reg cpu_ready_sync1, cpu_ready_sync2;
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
            cpu_ready_sync1 <= rst_cpu_sync;
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_230145_632624_082334__sample_4
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;
    
    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end
    
    // 2-flop synchronizer for CPU reset
    reg cpu_ready_sync1, cpu_ready_sync2;
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
            cpu_ready_sync1 <= rst_cpu_sync;
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_141859_833435_7c9834__sample_4
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;
    
    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end
    
    // 2-flop synchronizer for CPU reset
    reg cpu_ready_sync1, cpu_ready_sync2;
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
            cpu_ready_sync1 <= rst_cpu_sync;
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_172135_562392_bd9fc2__sample_5
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg rst_bus_sync_d1;
    reg rst_bus_sync_d2;

    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            rst_bus_sync_d1 <= 1'b1;
            rst_bus_sync_d2 <= 1'b1;
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_230145_632624_082334__sample_5
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg rst_cpu_ready_sync;
    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_ready_sync <= 1'b1;
        end else begin
            rst_cpu_ready_sync <= rst_cpu_sync;
        end
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_141859_833435_7c9834__sample_5
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;
    
    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end
    
    // 2-flop synchronizer for CPU reset
    reg cpu_ready_sync1, cpu_ready_sync2;
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
            cpu_ready_sync1 <= rst_cpu_sync;
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260424_172135_562392_bd9fc2 ok failed failed skipped failed syntax /data/eval/out/run_20260424_172135_562392_bd9fc2/tmp/qwen3_coder_30b/06_reset_domain_crossing__task_62/sample_6/generated.v:42: error: 'rst_bus_ready_sync' has already been declared in this scope.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_172135_562392_bd9fc2__sample_6
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg rst_cpu_ready_sync;
    reg rst_bus_ready_sync;

    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_ready_sync <= 1'b1;
            rst_bus_sync <= 1'b1;
...
syntax details 
[stderr]
/data/eval/out/run_20260424_172135_562392_bd9fc2/tmp/qwen3_coder_30b/06_reset_domain_crossing__task_62/sample_6/generated.v:42: error: 'rst_bus_ready_sync' has already been declared in this scope.
/data/eval/out/run_20260424_172135_562392_bd9fc2/tmp/qwen3_coder_30b/06_reset_domain_crossing__task_62/sample_6/generated.v:27:      : It was declared here as a variable.
functional details 
[stderr]
/data/eval/out/run_20260424_172135_562392_bd9fc2/tmp/qwen3_coder_30b/06_reset_domain_crossing__task_62/sample_6/functional/generated.v:42: error: 'rst_bus_ready_sync' has already been declared in this scope.
/data/eval/out/run_20260424_172135_562392_bd9fc2/tmp/qwen3_coder_30b/06_reset_domain_crossing__task_62/sample_6/functional/generated.v:27:      : It was declared here as a variable.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260424_172135_562392_bd9fc2/tmp/qwen3_coder_30b/06_reset_domain_crossing__task_62/sample_6/generated.v:42: error: 'rst_bus_ready_sync' has already been declared in this scope.\n/data/eval/out/run_20260424_172135_562392_bd9fc2/tmp/qwen3_coder_30b/06_reset_domain_crossing__task_62/sample_6/generated.v:27:      : It was declared here as a variable.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260424_172135_562392_bd9fc2/tmp/qwen3_coder_30b/06_reset_domain_crossing__task_62/sample_6/functional/generated.v:42: error: 'rst_bus_ready_sync' has already been declared in this scope.\n/data/eval/out/run_20260424_172135_562392_bd9fc2/tmp/qwen3_coder_30b/06_reset_domain_crossing__task_62/sample_6/functional/generated.v:27:      : It was declared here as a variable.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_230145_632624_082334__sample_6
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg cpu_ready_sync1;
    reg cpu_ready_sync2;
    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_141859_833435_7c9834__sample_6
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg rst_cpu_ready_sync;
    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_ready_sync <= 1'b1;
        end else begin
            rst_cpu_ready_sync <= rst_cpu_sync;
        end
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_172135_562392_bd9fc2__sample_7
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg rst_cpu_ready_sync;
    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_ready_sync <= 1'b1;
        end else begin
            rst_cpu_ready_sync <= rst_cpu_sync;
        end
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_230145_632624_082334__sample_7
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg cpu_ready_sync1;
    reg cpu_ready_sync2;
    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_141859_833435_7c9834__sample_7
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg cpu_ready_sync1;
    reg cpu_ready_sync2;
    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_172135_562392_bd9fc2__sample_8
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg rst_bus_sync_d1;
    reg rst_bus_sync_d2;

    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            rst_bus_sync_d1 <= 1'b1;
            rst_bus_sync_d2 <= 1'b1;
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: BUS reset released after one synchronizer stage.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_230145_632624_082334__sample_8
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n)
            rst_cpu_sync <= 1'b1;
        else
            rst_cpu_sync <= 1'b0;
    end

    // Bus domain reset logic
    reg rst_cpu_ready_sync;
    reg rst_bus_ready_sync;

    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n)
            rst_cpu_ready_sync <= 1'b1;
        else
            rst_cpu_ready_sync <= rst_cpu_sync;
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_141859_833435_7c9834 ok failed failed skipped failed syntax /data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/pashencev__06_reset_domain_crossing__task_62/sample_8/generated.v:41: error: 'rst_bus_ready_sync' has already been declared in this scope.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_141859_833435_7c9834__sample_8
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n)
            rst_cpu_sync <= 1'b1;
        else
            rst_cpu_sync <= 1'b0;
    end

    // Bus domain reset logic
    reg rst_cpu_ready_sync;
    reg rst_bus_ready_sync;

    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_ready_sync <= 1'b1;
            rst_bus_sync <= 1'b1;
        end else begin
...
syntax details 
[stderr]
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/pashencev__06_reset_domain_crossing__task_62/sample_8/generated.v:41: error: 'rst_bus_ready_sync' has already been declared in this scope.
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/pashencev__06_reset_domain_crossing__task_62/sample_8/generated.v:26:      : It was declared here as a variable.
functional details 
[stderr]
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/pashencev__06_reset_domain_crossing__task_62/sample_8/functional/generated.v:41: error: 'rst_bus_ready_sync' has already been declared in this scope.
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/pashencev__06_reset_domain_crossing__task_62/sample_8/functional/generated.v:26:      : It was declared here as a variable.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/pashencev__06_reset_domain_crossing__task_62/sample_8/generated.v:41: error: 'rst_bus_ready_sync' has already been declared in this scope.\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/pashencev__06_reset_domain_crossing__task_62/sample_8/generated.v:26:      : It was declared here as a variable.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/pashencev__06_reset_domain_crossing__task_62/sample_8/functional/generated.v:41: error: 'rst_bus_ready_sync' has already been declared in this scope.\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/pashencev__06_reset_domain_crossing__task_62/sample_8/functional/generated.v:26:      : It was declared here as a variable.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_172135_562392_bd9fc2__sample_9
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg rst_cpu_ready_sync;
    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_ready_sync <= 1'b1;
        end else begin
            rst_cpu_ready_sync <= rst_cpu_sync;
        end
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_230145_632624_082334__sample_9
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg cpu_ready_sync1;
    reg cpu_ready_sync2;
    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_141859_833435_7c9834__sample_9
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n)
            rst_cpu_sync <= 1'b1;
        else
            rst_cpu_sync <= 1'b0;
    end

    // Bus domain reset logic
    reg rst_cpu_ready_sync;
    reg rst_bus_ready_sync;

    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n)
            rst_cpu_ready_sync <= 1'b1;
        else
            rst_cpu_ready_sync <= rst_cpu_sync;
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_172135_562392_bd9fc2__sample_10
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg cpu_ready_sync1;
    reg cpu_ready_sync2;
    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260424_230145_632624_082334__sample_10
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg cpu_ready_sync1;
    reg cpu_ready_sync2;
    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            cpu_ready_sync1 <= 1'b1;
            cpu_ready_sync2 <= 1'b1;
        end else begin
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_141859_833435_7c9834__sample_10
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // Internal signals for reset synchronization
    reg rst_cpu_sync;
    reg rst_bus_sync;
    reg rst_periph_sync;

    // CPU domain reset logic
    always @(posedge clk_cpu or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_sync <= 1'b1;
        end else begin
            rst_cpu_sync <= 1'b0;
        end
    end

    // Bus domain reset logic
    reg rst_cpu_ready_sync;
    always @(posedge clk_bus or negedge arst_n) begin
        if (!arst_n) begin
            rst_cpu_ready_sync <= 1'b1;
        end else begin
            rst_cpu_ready_sync <= rst_cpu_sync;
        end
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: PERIPH reset did not release after two synchronized stages.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}