qwen3-coder:30b | RAG on

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

reg srst_n_reg;
reg [1:0] delay_counter;
reg init_pulse_reg;

// Asynchronous assertion
assign srst_n = srst_n_reg;

// Initialize
always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        srst_n_reg <= 1'b0;
        delay_counter <= 2'b00;
        init_pulse_reg <= 1'b0;
    end else begin
        // Synchronous deassertion sequence
        if (delay_counter == 2'b00) begin
            // First flop of synchronizer
            delay_counter <= 2'b01;
        end else if (delay_counter == 2'b01) begin
            // Second flop of synchronizer
            if (arst_n) begin
                // Start delay counter if arst_n is high
                delay_counter <= 2'b10;
                init_pulse_reg <= 1'b1;
...

[error]
None

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

reg srst_n_reg;
reg [1:0] delay_counter;
reg init_pulse_reg;

// Asynchronous assertion
assign srst_n = srst_n_reg;

// Initialize
always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        srst_n_reg <= 1'b0;
        delay_counter <= 2'b00;
        init_pulse_reg <= 1'b0;
    end else begin
        // Synchronous deassertion sequence
        if (delay_counter == 2'b00) begin
            // First flop of synchronizer
            delay_counter <= 2'b01;
        end else if (delay_counter == 2'b01) begin
            // Second flop of synchronizer
            if (arst_n) begin
                // Check if we should delay release
                if (release_delay != 2'b00) begin
                    delay_counter <= release_delay;
...

[stdout]
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset did not release with a one-cycle init pulse after the full delay.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

reg srst_n_reg;
reg [1:0] delay_counter;
reg init_pulse_reg;

// Asynchronous assertion
assign srst_n = srst_n_reg;

// Initialize init_pulse
assign init_pulse = init_pulse_reg;

always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        // Asynchronous assertion
        srst_n_reg <= 1'b0;
        delay_counter <= 2'b00;
        init_pulse_reg <= 1'b0;
    end else begin
        // Synchronous deassertion sequence
        case (delay_counter)
            2'b00: begin
                // First flop of synchronizer
                delay_counter <= 2'b01;
            end
            2'b01: begin
...

[stdout]
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: delay=0 init_pulse lasted too long.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released before the extra delay window started.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;
    reg rst_release_en;
    reg rst_release_en_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // Detect rising edge of sync_arst_n
    always @(posedge clk) begin
...

[error]
None

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;
    reg reset_release_req;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // Detect rising edge of sync_arst_n
    reg arst_n_rising_edge;
    always @(posedge clk) begin
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;
    reg rst_release_en;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // Reset release enable logic
    always @(posedge clk) begin
        if (!arst_n)
...

[error]
None

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;
    reg rst_release_en;
    reg rst_release_en_q;

    // Asynchronous assertion
    always @(negedge arst_n or posedge clk) begin
        if (arst_n == 1'b0) begin
            srst_n_int <= 1'b0;
            init_pulse_int <= 1'b0;
        end else begin
            // Synchronous deassertion
            if (sync_arst_n == 1'b1 && sync_arst_n_q == 1'b0) begin
                rst_release_en <= 1'b1;
                delay_cnt <= release_delay;
            end else if (rst_release_en == 1'b1) begin
                if (delay_cnt == 0) begin
                    srst_n_int <= 1'b1;
                    init_pulse_int <= 1'b1;
                    rst_release_en <= 1'b0;
                end else begin
...

[stdout]
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: init_pulse was not exactly one cycle wide.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;
    reg rst_release_req;
    reg rst_release_req_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // Detect rising edge of sync_arst_n
    always @(posedge clk) begin
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;
    reg rst_release_req;
    reg rst_release_req_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // Detect rising edge of sync_arst_n
    always @(posedge clk) begin
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;
    reg reset_release_req;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // Detect rising edge of sync_arst_n
    reg arst_n_rising_edge;
    always @(posedge clk) begin
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;
    reg rst_release_en;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // Reset release enable logic
    always @(posedge clk) begin
        if (!arst_n)
...

[stdout]
ERROR: outputs were not properly reset.
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}

module delayed_reset_release (
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output srst_n,
    output init_pulse
);

    reg [1:0] delay_cnt;
    reg srst_n_int;
    reg init_pulse_int;
    reg sync_arst_n;
    reg sync_arst_n_q;

    // Synchronous assertion
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n)
            srst_n_int <= 1'b0;
        else
            srst_n_int <= 1'b1;
    end

    // 2-flop synchronizer for arst_n
    always @(posedge clk) begin
        sync_arst_n_q <= arst_n;
        sync_arst_n <= sync_arst_n_q;
    end

    // State machine for release delay
    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            delay_cnt <= 2'b00;
...

[stdout]
ERROR: reset released after only one synchronizer edge.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)

[error]
None

[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset released after only one synchronizer edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]

{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}