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qwen3-coder:30b | RAG on

07_csr_register_map_generation / task_70 | apb_timer_csr

benchmarkilyasov
task_idilyasov/07_csr_register_map_generation/task_70
samples_total33
final_success_samples3
final_success_rate_samples9.1%
functional_pass_rate_samples9.1%
synth_pass_rate_samples9.1%
source_runsrun_20260424_144121_405769_1acdc5, run_20260424_172135_562392_bd9fc2, run_20260424_230145_632624_082334, run_20260426_141859_833435_7c9834

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260424_144121_405769_1acdc5 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_144121_405769_1acdc5__sample_1
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output reg timer_enable,
    output reg [7:0] threshold,
    output reg clear_done_pulse,
    output reg irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] ctrl_wdata;
reg [31:0] irq_wdata;
reg [31:0] cmd_wdata;

reg ctrl_we;
reg irq_we;
reg cmd_we;
...
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_1 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_172135_562392_bd9fc2__sample_1
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output reg timer_enable,
    output reg [7:0] threshold,
    output reg clear_done_pulse,
    output reg irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] ctrl_wdata;
reg [31:0] irq_wdata;
reg [31:0] cmd_wdata;

reg ctrl_we;
reg irq_we;
reg cmd_we;
...
functional details 
[stdout]
ERROR: reset values are incorrect.
ERROR: partial write to CTRL byte 0 corrupted threshold or failed enable.
ERROR: partial write to CTRL byte 1 failed.
ERROR: reserved bytes unexpectedly modified CTRL.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_1 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_230145_632624_082334__sample_1
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output reg timer_enable,
    output reg [7:0] threshold,
    output reg clear_done_pulse,
    output reg irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] ctrl_wdata;
reg [31:0] irq_wdata;
reg [31:0] cmd_wdata;

reg ctrl_we;
reg irq_we;
reg cmd_we;
...
functional details 
[stdout]
ERROR: reset values are incorrect.
ERROR: partial write to CTRL byte 0 corrupted threshold or failed enable.
ERROR: partial write to CTRL byte 1 failed.
ERROR: reserved bytes unexpectedly modified CTRL.
ERROR: writing 0 incorrectly cleared a W1C bit.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_1 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260426_141859_833435_7c9834__sample_1
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output reg timer_enable,
    output reg [7:0] threshold,
    output reg clear_done_pulse,
    output reg irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] ctrl_wdata;
reg [31:0] irq_wdata;
reg [31:0] cmd_wdata;

reg ctrl_we;
reg irq_we;
reg cmd_we;
...
functional details 
[stdout]
ERROR: reset values are incorrect.
ERROR: partial write to CTRL byte 0 corrupted threshold or failed enable.
ERROR: partial write to CTRL byte 1 failed.
ERROR: reserved bytes unexpectedly modified CTRL.
ERROR: STATUS readback failed. Got 00000000
ERROR: writing 0 incorrectly cleared a W1C bit.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260424_144121_405769_1acdc5 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_144121_405769_1acdc5__sample_2
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
wire [31:0] wdata;

reg clear_done_pulse_reg;

assign wdata = pwdata;
assign prdata = rdata;
assign pready = 1;
...
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_2 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_172135_562392_bd9fc2__sample_2
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: done sticky bit was not set by timer_done_evt.
ERROR: writing 0 incorrectly cleared a W1C bit.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_230145_632624_082334__sample_2
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
wire [31:0] wdata;

reg clear_done_pulse_reg;

assign wdata = pwdata;
assign prdata = rdata;
assign pready = 1;
...
functional details 
[stdout]
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260426_141859_833435_7c9834__sample_2
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: done sticky bit was not set by timer_done_evt.
ERROR: writing 0 incorrectly cleared a W1C bit.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260424_144121_405769_1acdc5 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_144121_405769_1acdc5__sample_3
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output reg timer_enable,
    output reg [7:0] threshold,
    output reg clear_done_pulse,
    output reg irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] ctrl_reg_w;
reg [31:0] irq_status_reg_w;
reg [31:0] cmd_reg_w;

reg ctrl_write;
reg irq_status_write;
reg cmd_write;
...
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_3 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_172135_562392_bd9fc2__sample_3
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
wire [31:0] wdata;

reg clear_done_pulse_reg;

assign wdata = pwdata;
assign prdata = rdata;
assign pready = 1;
...
functional details 
[stdout]
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_230145_632624_082334__sample_3
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: done sticky bit was not set by timer_done_evt.
ERROR: writing 0 incorrectly cleared a W1C bit.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260426_141859_833435_7c9834__sample_3
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
wire [31:0] wdata;

reg clear_done_pulse_reg;

assign wdata = pwdata;
assign prdata = rdata;
assign pready = 1;
...
functional details 
[stdout]
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: clear_done_pulse was not asserted on CMD write.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_172135_562392_bd9fc2__sample_4
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: clear_done_pulse was not asserted on CMD write.
ERROR: clear_done_pulse lasted longer than one cycle.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: clear_done_pulse was not asserted on CMD write.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_230145_632624_082334__sample_4
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: done sticky bit was not set by timer_done_evt.
ERROR: writing 0 incorrectly cleared a W1C bit.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260426_141859_833435_7c9834__sample_4
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output reg timer_enable,
    output reg [7:0] threshold,
    output reg clear_done_pulse,
    output reg irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] ctrl_wdata;
reg [31:0] irq_wdata;
reg [31:0] cmd_wdata;

reg ctrl_write;
reg irq_write;
reg cmd_write;
...
functional details 
[stdout]
ERROR: reset values are incorrect.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_172135_562392_bd9fc2__sample_5
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_230145_632624_082334__sample_5
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
wire [31:0] wdata;

reg clear_done_pulse_reg;

assign wdata = pwdata;
assign prdata = rdata;
assign pready = 1;
...
functional details 
[stdout]
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260426_141859_833435_7c9834__sample_5
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: done sticky bit was not set by timer_done_evt.
ERROR: writing 0 incorrectly cleared a W1C bit.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_172135_562392_bd9fc2__sample_6
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_230145_632624_082334__sample_6
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output reg timer_enable,
    output reg [7:0] threshold,
    output reg clear_done_pulse,
    output reg irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] reg_write_data;
reg reg_write_enable;

always @(*) begin
    reg_write_data = pwdata;
    reg_write_enable = 0;
    
    if (psel && penable && pwrite) begin
...
functional details 
[stdout]
ERROR: reset values are incorrect.
ERROR: partial write to CTRL byte 0 corrupted threshold or failed enable.
ERROR: partial write to CTRL byte 1 failed.
ERROR: writing 1 failed to clear IRQ_STATUS.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260426_141859_833435_7c9834__sample_6
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: done sticky bit was not set by timer_done_evt.
ERROR: writing 0 incorrectly cleared a W1C bit.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_172135_562392_bd9fc2__sample_7
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
wire [31:0] wdata;

reg clear_done_pulse_reg;

assign wdata = pwdata;
assign prdata = rdata;
assign pready = 1;
...
functional details 
[stdout]
ERROR: done sticky bit was not set by timer_done_evt.
ERROR: writing 0 incorrectly cleared a W1C bit.
ERROR: clear_done_pulse lasted longer than one cycle.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_230145_632624_082334__sample_7
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
wire [31:0] wdata;

reg clear_done_pulse_reg;

assign wdata = pwdata;
assign prdata = rdata;
assign pready = 1;
...
functional details 
[stdout]
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260426_141859_833435_7c9834__sample_7
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_172135_562392_bd9fc2__sample_8
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_230145_632624_082334__sample_8
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output reg timer_enable,
    output reg [7:0] threshold,
    output reg clear_done_pulse,
    output reg irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] ctrl_wdata;
reg [31:0] irq_wdata;
reg [31:0] cmd_wdata;

reg ctrl_write;
reg irq_write;
reg cmd_write;
...
functional details 
[stdout]
ERROR: reset values are incorrect.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260426_141859_833435_7c9834__sample_8
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
wire [31:0] wdata;

reg clear_done_pulse_reg;

assign wdata = pwdata;
assign prdata = rdata;
assign pready = 1;
...
functional details 
[stdout]
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_172135_562392_bd9fc2__sample_9
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output reg [31:0] prdata,
    output reg pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output reg timer_enable,
    output reg [7:0] threshold,
    output reg clear_done_pulse,
    output reg irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] reg_write_data;
reg reg_write_enable;

always @(*) begin
    reg_write_data = pwdata;
    reg_write_enable = 0;
    
    if (psel && penable && pwrite) begin
...
functional details 
[stdout]
ERROR: reset values are incorrect.
ERROR: partial write to CTRL byte 0 corrupted threshold or failed enable.
ERROR: partial write to CTRL byte 1 failed.
ERROR: writing 1 failed to clear IRQ_STATUS.
ERROR: clear_done_pulse lasted longer than one cycle.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_230145_632624_082334__sample_9
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: done sticky bit was not set by timer_done_evt.
ERROR: writing 0 incorrectly cleared a W1C bit.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260426_141859_833435_7c9834__sample_9
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
wire [31:0] wdata;

reg clear_done_pulse_reg;

assign wdata = pwdata;
assign prdata = rdata;
assign pready = 1;
...
functional details 
[stdout]
ERROR: done sticky bit was not set by timer_done_evt.
ERROR: writing 0 incorrectly cleared a W1C bit.
ERROR: clear_done_pulse lasted longer than one cycle.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260424_172135_562392_bd9fc2 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_172135_562392_bd9fc2__sample_10
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CMD register should read back as zero.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260424_230145_632624_082334 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260424_230145_632624_082334__sample_10
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: done sticky bit was not set by timer_done_evt.
ERROR: writing 0 incorrectly cleared a W1C bit.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_141859_833435_7c9834 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_70\samples\run_20260426_141859_833435_7c9834__sample_10
generated.v preview 
module apb_timer_csr (
    input clk,
    input rst_n,
    input psel,
    input penable,
    input pwrite,
    input [7:0] paddr,
    input [31:0] pwdata,
    input [3:0] pstrb,
    output [31:0] prdata,
    output pready,
    input [7:0] hw_status,
    input timer_done_evt,
    output timer_enable,
    output [7:0] threshold,
    output clear_done_pulse,
    output irq_pending
);

reg [31:0] ctrl_reg;
reg [31:0] status_reg;
reg [31:0] irq_status_reg;
reg [31:0] cmd_reg;

reg [31:0] rdata;
reg pready_out;
reg clear_done_pulse_out;

// Register write logic
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        ctrl_reg <= 32'h1000;
...
functional details 
[stdout]
ERROR: done sticky bit was not set by timer_done_evt.
ERROR: writing 0 incorrectly cleared a W1C bit.
ERROR: CMD register should read back as zero.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_70/tb.v:187: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: done sticky bit was not set by timer_done_evt.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}