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qwen3-coder:30b | RAG on

13_rtllm_arithmetic / task_06 | verified_adder_64bit

benchmarkrtllm
task_idrtllm/13_rtllm_arithmetic/task_06
samples_total31
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260424_203453_201510_6e98ce, run_20260424_212142_473417_af1ca5, run_20260424_230145_632624_082334, run_20260426_141859_833435_7c9834

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260424_203453_201510_6e98ce ok failed failed skipped failed syntax rified_adder_64bit.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_1
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    wire [64:0] sum_pipe0, sum_pipe1, sum_pipe2;
    wire [64:0] carry_pipe0, carry_pipe1, carry_pipe2;
    wire i_en_reg0, i_en_reg1, i_en_reg2;
    
    // Pipeline registers for input enable signal
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            i_en_reg0 <= 1'b0;
            i_en_reg1 <= 1'b0;
            i_en_reg2 <= 1'b0;
        end else begin
            i_en_reg0 <= i_en;
            i_en_reg1 <= i_en_reg0;
            i_en_reg2 <= i_en_reg1;
        end
    end
    
    // First pipeline stage
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            sum_pipe0 <= 0;
            carry_pipe0 <= 0;
...
syntax details 
[stderr]
rified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:11:      : sum_pipe1 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:46: error: carry_pipe1 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:12:      : carry_pipe1 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:53: error: sum_pipe2 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:11:      : sum_pipe2 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:54: error: carry_pipe2 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:12:      : carry_pipe2 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:56: error: sum_pipe2 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:11:      : sum_pipe2 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:57: error: carry_pipe2 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:12:      : carry_pipe2 is declared here as wire.
18 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "rified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:11:      : sum_pipe1 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:46: error: carry_pipe1 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:12:      : carry_pipe1 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:53: error: sum_pipe2 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:11:      : sum_pipe2 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:54: error: carry_pipe2 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:12:      : carry_pipe2 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:56: error: sum_pipe2 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:11:      : sum_pipe2 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:57: error: carry_pipe2 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_1/generated.v:12:      : carry_pipe2 is declared here as wire.\n18 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_1 run_20260424_212142_473417_af1ca5 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_212142_473417_af1ca5__sample_1
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
            sum_pipe0 <= 0;
            sum_pipe1 <= 0;
            sum_pipe2 <= 0;
            sum_pipe3 <= 0;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_1 run_20260424_230145_632624_082334 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_1
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Pipeline stage 0
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
            adda_reg <= adda;
            addb_reg <= addb;
            i_en_reg <= i_en;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_1 run_20260426_141859_833435_7c9834 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_141859_833435_7c9834__sample_1
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    
    reg o_en_reg;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
            sum_pipe0 <= 0;
            sum_pipe1 <= 0;
            sum_pipe2 <= 0;
            sum_pipe3 <= 0;
            o_en_reg <= 0;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260424_203453_201510_6e98ce ok failed failed skipped failed syntax er_64bit.gen_full_adder[62].genblk1'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_2
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_reg;
    reg [64:0] carry_reg;
    
    wire [64:0] sum;
    wire [64:0] carry;
    
    wire [64:0] adda_pipe;
    wire [64:0] addb_pipe;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
            adda_reg <= adda;
            addb_reg <= addb;
...
syntax details 
[stderr]
er_64bit.gen_full_adder[62].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:67: error: o_en is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:8:      : o_en is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:69: error: o_en is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:8:      : o_en is declared here as wire.
130 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "er_64bit.gen_full_adder[62].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:67: error: o_en is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:8:      : o_en is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:69: error: o_en is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_2/generated.v:8:      : o_en is declared here as wire.\n130 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260424_230145_632624_082334 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_2
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    
    reg o_en_reg;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
            sum_pipe0 <= 0;
            sum_pipe1 <= 0;
            sum_pipe2 <= 0;
            sum_pipe3 <= 0;
            o_en_reg <= 0;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_141859_833435_7c9834 ok failed failed skipped failed syntax 9_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[61].genblk1'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_141859_833435_7c9834__sample_2
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_reg;
    reg [64:0] carry_reg;
    
    wire [64:0] sum;
    wire [64:0] carry;
    
    wire [64:0] adda_pipe;
    wire [64:0] addb_pipe;
    
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
...
syntax details 
[stderr]
9_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[61].genblk1'
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[62].genblk1'
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
128 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "9_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[61].genblk1'\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[62].genblk1'\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_2/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n128 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260424_203453_201510_6e98ce ok failed failed skipped failed syntax er_64bit.gen_full_adder[62].genblk1'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_3
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_reg;
    reg [64:0] carry_reg;
    
    wire [64:0] sum;
    wire [64:0] carry;
    
    wire [64:0] adda_pipe;
    wire [64:0] addb_pipe;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
            adda_reg <= adda;
            addb_reg <= addb;
...
syntax details 
[stderr]
er_64bit.gen_full_adder[62].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:67: error: o_en is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:8:      : o_en is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:69: error: o_en is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:8:      : o_en is declared here as wire.
130 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "er_64bit.gen_full_adder[62].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:67: error: o_en is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:8:      : o_en is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:69: error: o_en is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_3/generated.v:8:      : o_en is declared here as wire.\n130 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260424_230145_632624_082334 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_3
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
            sum_pipe0 <= 0;
            sum_pipe1 <= 0;
            sum_pipe2 <= 0;
            sum_pipe3 <= 0;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_141859_833435_7c9834 ok failed failed skipped failed syntax 9_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[61].genblk1'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_141859_833435_7c9834__sample_3
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_reg;
    reg [64:0] carry_reg;
    
    wire [64:0] sum;
    wire [64:0] carry;
    
    wire [64:0] adda_pipe;
    wire [64:0] addb_pipe;
    
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
...
syntax details 
[stderr]
9_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[61].genblk1'
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[62].genblk1'
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
128 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "9_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[61].genblk1'\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[62].genblk1'\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_3/generated.v:52: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n128 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260424_203453_201510_6e98ce ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_4
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Pipeline stage 0
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
            adda_reg <= adda;
            addb_reg <= addb;
            i_en_reg <= i_en;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260424_230145_632624_082334 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_4
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
            sum_pipe0 <= 0;
            sum_pipe1 <= 0;
            sum_pipe2 <= 0;
            sum_pipe3 <= 0;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_141859_833435_7c9834 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_141859_833435_7c9834__sample_4
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Pipeline stage 0
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
            adda_reg <= adda;
            addb_reg <= addb;
            i_en_reg <= i_en;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260424_203453_201510_6e98ce ok failed failed skipped failed syntax er_64bit.gen_full_adder[62].genblk1'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_5
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_reg;
    reg [64:0] carry_reg;
    
    wire [64:0] sum;
    wire [64:0] carry;
    
    wire [64:0] adda_pipe;
    wire [64:0] addb_pipe;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
            adda_reg <= adda;
            addb_reg <= addb;
...
syntax details 
[stderr]
er_64bit.gen_full_adder[62].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:67: error: o_en is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:8:      : o_en is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:69: error: o_en is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:8:      : o_en is declared here as wire.
130 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "er_64bit.gen_full_adder[62].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:67: error: o_en is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:8:      : o_en is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:69: error: o_en is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_5/generated.v:8:      : o_en is declared here as wire.\n130 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260424_230145_632624_082334 ok failed failed skipped failed syntax 4_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_5
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_reg;
    reg [64:0] carry_reg;
    
    wire [64:0] sum;
    wire [64:0] carry;
    
    wire [64:0] adda_pipe;
    wire [64:0] addb_pipe;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
            adda_reg <= adda;
            addb_reg <= addb;
...
syntax details 
[stderr]
4_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:67: error: o_en is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:8:      : o_en is declared here as wire.
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:69: error: o_en is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:8:      : o_en is declared here as wire.
130 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "4_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:67: error: o_en is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:8:      : o_en is declared here as wire.\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:69: error: o_en is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_5/generated.v:8:      : o_en is declared here as wire.\n130 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_141859_833435_7c9834 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_141859_833435_7c9834__sample_5
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
            sum_pipe0 <= 0;
            sum_pipe1 <= 0;
            sum_pipe2 <= 0;
            sum_pipe3 <= 0;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260424_203453_201510_6e98ce ok failed failed skipped failed syntax er_64bit.gen_full_adder[62].genblk1'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_6
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_reg;
    reg [64:0] carry_reg;
    
    wire [64:0] sum;
    wire [64:0] carry;
    
    wire [64:0] adda_pipe;
    wire [64:0] addb_pipe;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
            adda_reg <= adda;
            addb_reg <= addb;
...
syntax details 
[stderr]
er_64bit.gen_full_adder[62].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:67: error: o_en is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:8:      : o_en is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:69: error: o_en is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:8:      : o_en is declared here as wire.
130 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "er_64bit.gen_full_adder[62].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:67: error: o_en is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:8:      : o_en is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:69: error: o_en is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_6/generated.v:8:      : o_en is declared here as wire.\n130 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260424_230145_632624_082334 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_6
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
            sum_pipe0 <= 0;
            sum_pipe1 <= 0;
            sum_pipe2 <= 0;
            sum_pipe3 <= 0;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_141859_833435_7c9834 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_141859_833435_7c9834__sample_6
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_reg;
    reg [64:0] carry_reg;
    
    wire [64:0] sum;
    wire [64:0] carry;
    
    wire [64:0] adda_pipe;
    wire [64:0] addb_pipe;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
            adda_reg <= adda;
            addb_reg <= addb;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260424_203453_201510_6e98ce ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_7
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    reg [64:0] sum_pipe4;
    reg [64:0] sum_pipe5;
    reg [64:0] sum_pipe6;
    reg [64:0] sum_pipe7;
    
    reg o_en_reg;
    
    // Pipeline register updates
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260424_230145_632624_082334 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_7
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
            sum_pipe0 <= 0;
            sum_pipe1 <= 0;
            sum_pipe2 <= 0;
            sum_pipe3 <= 0;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_141859_833435_7c9834 ok failed failed skipped failed syntax 9_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[61].genblk1'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_141859_833435_7c9834__sample_7
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_reg;
    reg [64:0] carry_reg;
    
    wire [64:0] sum;
    wire [64:0] carry;
    
    wire [64:0] adda_pipe;
    wire [64:0] addb_pipe;
    
    reg o_en_reg;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
...
syntax details 
[stderr]
9_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[61].genblk1'
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[62].genblk1'
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'
/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
128 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "9_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[61].genblk1'\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[62].genblk1'\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'\n/data/eval/out/run_20260426_141859_833435_7c9834/tmp/qwen_coder_30/rtllm__13_rtllm_arithmetic__task_06/sample_7/generated.v:51: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n128 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260424_203453_201510_6e98ce ok failed failed skipped failed syntax rified_adder_64bit.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_8
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    wire [64:0] sum_pipe0, sum_pipe1, sum_pipe2;
    wire [64:0] carry_pipe0, carry_pipe1, carry_pipe2;
    wire i_en_reg0, i_en_reg1, i_en_reg2;
    
    // Pipeline registers for input enable signal
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            i_en_reg0 <= 1'b0;
        else
            i_en_reg0 <= i_en;
    end
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            i_en_reg1 <= 1'b0;
        else
            i_en_reg1 <= i_en_reg0;
    end
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            i_en_reg2 <= 1'b0;
...
syntax details 
[stderr]
rified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:11:      : sum_pipe1 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:55: error: carry_pipe1 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:12:      : carry_pipe1 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:62: error: sum_pipe2 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:11:      : sum_pipe2 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:63: error: carry_pipe2 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:12:      : carry_pipe2 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:65: error: sum_pipe2 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:11:      : sum_pipe2 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:66: error: carry_pipe2 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:12:      : carry_pipe2 is declared here as wire.
18 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "rified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:11:      : sum_pipe1 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:55: error: carry_pipe1 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:12:      : carry_pipe1 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:62: error: sum_pipe2 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:11:      : sum_pipe2 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:63: error: carry_pipe2 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:12:      : carry_pipe2 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:65: error: sum_pipe2 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:11:      : sum_pipe2 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:66: error: carry_pipe2 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_8/generated.v:12:      : carry_pipe2 is declared here as wire.\n18 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260424_230145_632624_082334 ok failed failed skipped failed syntax Unknown module type: full_adder
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_8
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_reg;
    reg [64:0] carry_reg;
    
    wire [64:0] sum;
    wire [64:0] carry;
    
    // Pipeline registers
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Full adder for each bit
    wire [64:0] carry_out;
    
    // Generate full adder for each bit
    genvar i;
    for (i = 0; i < 64; i = i + 1) begin : gen_full_adder
        full_adder fa (
            .a(adda_reg[i]),
...
syntax details 
[stderr]
Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder
64 error(s) during elaboration.
*** These modules were missing:
        full_adder referenced 64 times.
***
functional details 
[stderr]
/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder
67 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
        full_adder referenced 64 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": " Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/generated.v:31: error: Unknown module type: full_adder\n64 error(s) during elaboration.\n*** These modules were missing:\n        full_adder referenced 64 times.\n***\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown module type: full_adder\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_8/functional/generated.v:31: error: Unknown mo…
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_141859_833435_7c9834 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_141859_833435_7c9834__sample_8
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
            sum_pipe0 <= 0;
            sum_pipe1 <= 0;
            sum_pipe2 <= 0;
            sum_pipe3 <= 0;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260424_203453_201510_6e98ce ok failed failed skipped failed syntax rified_adder_64bit.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_9
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    wire [64:0] sum_pipe0, sum_pipe1, sum_pipe2;
    wire [64:0] carry_pipe0, carry_pipe1, carry_pipe2;
    wire i_en_reg0, i_en_reg1, i_en_reg2;
    
    // Pipeline registers for input enable signal
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            i_en_reg0 <= 1'b0;
        else
            i_en_reg0 <= i_en;
    end
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            i_en_reg1 <= 1'b0;
        else
            i_en_reg1 <= i_en_reg0;
    end
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            i_en_reg2 <= 1'b0;
...
syntax details 
[stderr]
rified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:11:      : sum_pipe1 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:55: error: carry_pipe1 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:12:      : carry_pipe1 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:62: error: sum_pipe2 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:11:      : sum_pipe2 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:63: error: carry_pipe2 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:12:      : carry_pipe2 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:65: error: sum_pipe2 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:11:      : sum_pipe2 is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:66: error: carry_pipe2 is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:12:      : carry_pipe2 is declared here as wire.
18 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "rified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:11:      : sum_pipe1 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:55: error: carry_pipe1 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:12:      : carry_pipe1 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:62: error: sum_pipe2 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:11:      : sum_pipe2 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:63: error: carry_pipe2 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:12:      : carry_pipe2 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:65: error: sum_pipe2 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:11:      : sum_pipe2 is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:66: error: carry_pipe2 is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_9/generated.v:12:      : carry_pipe2 is declared here as wire.\n18 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260424_230145_632624_082334 ok failed failed skipped failed syntax 4_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_9
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_reg;
    reg [64:0] carry_reg;
    
    wire [64:0] sum;
    wire [64:0] carry;
    
    wire [64:0] adda_pipe;
    wire [64:0] addb_pipe;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
            adda_reg <= adda;
            addb_reg <= addb;
...
syntax details 
[stderr]
4_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:67: error: o_en is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:8:      : o_en is declared here as wire.
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:69: error: o_en is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:8:      : o_en is declared here as wire.
130 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "4_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:67: error: o_en is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:8:      : o_en is declared here as wire.\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:69: error: o_en is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_230145_632624_082334/tmp/qwen3_coder_30b/rtllm__13_rtllm_arithmetic__task_06/sample_9/generated.v:8:      : o_en is declared here as wire.\n130 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_141859_833435_7c9834 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_141859_833435_7c9834__sample_9
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Pipeline stage 0
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
            adda_reg <= adda;
            addb_reg <= addb;
            i_en_reg <= i_en;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260424_203453_201510_6e98ce ok failed failed skipped failed syntax gen_full_adder[62].genblk1'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_10
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_reg;
    reg [64:0] carry_reg;
    
    wire [64:0] sum;
    wire [64:0] carry;
    
    wire [64:0] adda_pipe;
    wire [64:0] addb_pipe;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
            adda_reg <= adda;
            addb_reg <= addb;
...
syntax details 
[stderr]
gen_full_adder[62].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:67: error: o_en is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:8:      : o_en is declared here as wire.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:69: error: o_en is not a valid l-value in verified_adder_64bit.
/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:8:      : o_en is declared here as wire.
130 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "gen_full_adder[62].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[63].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:49: error: Unable to bind wire/reg/memory `b_pipe[i]' in `verified_adder_64bit.gen_full_adder[64].genblk1'\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:49: error: Unable to elaborate r-value: (((adda_pipe[i])&(addb_pipe[i]))|((adda_pipe[i])&(carry[(i)-('sd1)])))|((b_pipe[i])&(carry[(i)-('sd1)]))\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:67: error: o_en is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:8:      : o_en is declared here as wire.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:69: error: o_en is not a valid l-value in verified_adder_64bit.\n/data/eval/out/run_20260424_203453_201510_6e98ce/tmp/qwen3_coder_30b/13_rtllm_arithmetic__task_06/sample_10/generated.v:8:      : o_en is declared here as wire.\n130 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260424_230145_632624_082334 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_10
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_pipe0;
    reg [64:0] sum_pipe1;
    reg [64:0] sum_pipe2;
    reg [64:0] sum_pipe3;
    
    reg [64:0] result_reg;
    reg o_en_reg;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
            sum_pipe0 <= 0;
            sum_pipe1 <= 0;
            sum_pipe2 <= 0;
            sum_pipe3 <= 0;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_141859_833435_7c9834 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260426_141859_833435_7c9834__sample_10
generated.v preview 
module verified_adder_64bit(
    input clk,
    input rst_n,
    input i_en,
    input [63:0] adda,
    input [63:0] addb,
    output [64:0] result,
    output o_en
);

    reg [63:0] adda_reg;
    reg [63:0] addb_reg;
    reg i_en_reg;
    
    reg [64:0] sum_reg;
    reg [64:0] carry_reg;
    
    wire [64:0] sum;
    wire [64:0] carry;
    
    wire [64:0] adda_pipe;
    wire [64:0] addb_pipe;
    
    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            adda_reg <= 0;
            addb_reg <= 0;
            i_en_reg <= 0;
        end else begin
            adda_reg <= adda;
            addb_reg <= addb;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}